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ARM64: make sure FastISel emits SSA MachineInstrs

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We need to use a temporary register for a 2-step operation like REM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208297 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2014-05-08 10:30:56 +00:00
parent 89329e902c
commit 291cd09645
2 changed files with 23 additions and 11 deletions
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7
lib/Target/ARM64/ARM64FastISel.cpp
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@@ -1849,14 +1849,15 @@ bool ARM64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
if (!Src1Reg)
return false;
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), ResultReg)
unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
.addReg(Src0Reg)
.addReg(Src1Reg);
// The remainder is computed as numerator - (quotient * denominator) using the
// MSUB instruction.
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
.addReg(ResultReg)
.addReg(QuotReg)
.addReg(Src1Reg)
.addReg(Src0Reg);
UpdateValueMap(I, ResultReg);