mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-15 23:31:37 +00:00
80 column and whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92837 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
e10920d678
commit
2973b57093
@ -1,4 +1,4 @@
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//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
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//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -77,18 +77,18 @@ unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
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{
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assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
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assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
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// find group for each register
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unsigned Group1 = GetGroup(Reg1);
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unsigned Group2 = GetGroup(Reg2);
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// if either group is 0, then that must become the parent
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unsigned Parent = (Group1 == 0) ? Group1 : Group2;
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unsigned Other = (Parent == Group1) ? Group2 : Group1;
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GroupNodes.at(Other) = Parent;
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return Parent;
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}
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unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
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{
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// Create a new GroupNode for Reg. Reg's existing GroupNode must
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@ -111,7 +111,7 @@ bool AggressiveAntiDepState::IsLive(unsigned Reg)
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AggressiveAntiDepBreaker::
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AggressiveAntiDepBreaker(MachineFunction& MFi,
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TargetSubtarget::RegClassVector& CriticalPathRCs) :
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TargetSubtarget::RegClassVector& CriticalPathRCs) :
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AntiDepBreaker(), MF(MFi),
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MRI(MF.getRegInfo()),
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TRI(MF.getTarget().getRegisterInfo()),
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@ -126,9 +126,9 @@ AggressiveAntiDepBreaker(MachineFunction& MFi,
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else
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CriticalPathSet |= CPSet;
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}
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DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
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DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
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DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
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r = CriticalPathSet.find_next(r))
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dbgs() << " " << TRI->getName(r));
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DEBUG(dbgs() << '\n');
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@ -232,10 +232,11 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
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// schedule region).
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if (State->IsLive(Reg)) {
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DEBUG(if (State->GetGroup(Reg) != 0)
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dbgs() << " " << TRI->getName(Reg) << "=g" <<
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dbgs() << " " << TRI->getName(Reg) << "=g" <<
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State->GetGroup(Reg) << "->g0(region live-out)");
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State->UnionGroups(Reg, 0);
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} else if ((DefIndices[Reg] < InsertPosIndex) && (DefIndices[Reg] >= Count)) {
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} else if ((DefIndices[Reg] < InsertPosIndex)
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&& (DefIndices[Reg] >= Count)) {
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DefIndices[Reg] = Count;
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}
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}
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@ -266,7 +267,7 @@ void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
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if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
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IsImplicitDefUse(MI, MO)) {
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const unsigned Reg = MO.getReg();
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PassthruRegs.insert(Reg);
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@ -320,11 +321,12 @@ static SUnit *CriticalPathStep(SUnit *SU) {
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}
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void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
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const char *tag, const char *header,
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const char *tag,
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const char *header,
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const char *footer) {
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unsigned *KillIndices = State->GetKillIndices();
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unsigned *DefIndices = State->GetDefIndices();
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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if (!State->IsLive(Reg)) {
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@ -355,10 +357,12 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
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DEBUG(if ((header == NULL) && (footer != NULL)) dbgs() << footer);
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}
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void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count,
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std::set<unsigned>& PassthruRegs) {
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void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
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unsigned Count,
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std::set<unsigned>& PassthruRegs)
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{
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unsigned *DefIndices = State->GetDefIndices();
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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// Handle dead defs by simulating a last-use of the register just
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@ -371,7 +375,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou
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if (!MO.isReg() || !MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
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}
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@ -382,7 +386,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
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DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
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// If MI's defs have a special allocation requirement, don't allow
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// any def registers to be changed. Also assume all registers
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@ -398,11 +402,11 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou
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unsigned AliasReg = *Alias;
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if (State->IsLive(AliasReg)) {
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State->UnionGroups(Reg, AliasReg);
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DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
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DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
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TRI->getName(AliasReg) << ")");
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}
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}
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// Note register reference...
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const TargetRegisterClass *RC = NULL;
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if (i < MI->getDesc().getNumOperands())
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@ -438,7 +442,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Cou
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void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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unsigned Count) {
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DEBUG(dbgs() << "\tUse Groups:");
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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// Scan the register uses for this instruction and update
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@ -448,9 +452,9 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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if (!MO.isReg() || !MO.isUse()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
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State->GetGroup(Reg));
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DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
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State->GetGroup(Reg));
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// It wasn't previously live but now it is, this is a kill. Forget
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// the previous live-range information and start a new live-range
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@ -472,7 +476,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
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RegRefs.insert(std::make_pair(Reg, RR));
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}
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DEBUG(dbgs() << '\n');
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// Form a group of all defs and uses of a KILL instruction to ensure
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@ -486,7 +490,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (FirstReg != 0) {
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DEBUG(dbgs() << "=" << TRI->getName(Reg));
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State->UnionGroups(FirstReg, Reg);
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@ -495,7 +499,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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FirstReg = Reg;
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}
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}
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DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
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}
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}
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@ -507,13 +511,14 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
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// Check all references that need rewriting for Reg. For each, use
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// the corresponding register class to narrow the set of registers
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// that are appropriate for renaming.
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std::pair<std::multimap<unsigned,
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std::pair<std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator,
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std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator>
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Range = State->GetRegRefs().equal_range(Reg);
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for (std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>::iterator
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Q = Range.first, QE = Range.second; Q != QE; ++Q) {
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for (std::multimap<unsigned,
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AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first,
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QE = Range.second; Q != QE; ++Q) {
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const TargetRegisterClass *RC = Q->second.RC;
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if (RC == NULL) continue;
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@ -527,9 +532,9 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
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DEBUG(dbgs() << " " << RC->getName());
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}
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return BV;
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}
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}
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bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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unsigned AntiDepGroupIndex,
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@ -537,7 +542,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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std::map<unsigned, unsigned> &RenameMap) {
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unsigned *KillIndices = State->GetKillIndices();
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unsigned *DefIndices = State->GetDefIndices();
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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// Collect all referenced registers in the same group as
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@ -552,7 +557,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// Find the "superest" register in the group. At the same time,
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// collect the BitVector of registers that can be used to rename
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// each register.
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DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex << ":\n");
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DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
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<< ":\n");
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std::map<unsigned, BitVector> RenameRegisterMap;
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unsigned SuperReg = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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@ -563,7 +569,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// If Reg has any references, then collect possible rename regs
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if (RegRefs.count(Reg) > 0) {
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DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
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BitVector BV = GetRenameRegisters(Reg);
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RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
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@ -590,7 +596,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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static int renamecnt = 0;
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if (renamecnt++ % DebugDiv != DebugMod)
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return false;
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dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
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" for debug ***\n";
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}
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@ -600,9 +606,9 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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// order. If that register is available, and the corresponding
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// registers are available for the other group subregisters, then we
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// can use those registers to rename.
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const TargetRegisterClass *SuperRC =
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const TargetRegisterClass *SuperRC =
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TRI->getPhysicalRegisterRegClass(SuperReg, MVT::Other);
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const TargetRegisterClass::iterator RB = SuperRC->allocation_order_begin(MF);
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const TargetRegisterClass::iterator RE = SuperRC->allocation_order_end(MF);
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if (RB == RE) {
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@ -624,7 +630,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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const unsigned NewSuperReg = *R;
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// Don't replace a register with itself.
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if (NewSuperReg == SuperReg) continue;
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DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
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RenameMap.clear();
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@ -643,7 +649,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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}
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DEBUG(dbgs() << " " << TRI->getName(NewReg));
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// Check if Reg can be renamed to NewReg.
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BitVector BV = RenameRegisterMap[Reg];
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if (!BV.test(NewReg)) {
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@ -663,7 +669,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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for (const unsigned *Alias = TRI->getAliasSet(NewReg);
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*Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (State->IsLive(AliasReg) || (KillIndices[Reg] > DefIndices[AliasReg])) {
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if (State->IsLive(AliasReg) ||
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(KillIndices[Reg] > DefIndices[AliasReg])) {
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DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
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found = true;
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break;
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@ -672,11 +679,11 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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if (found)
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goto next_super_reg;
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}
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// Record that 'Reg' can be renamed to 'NewReg'.
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RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
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}
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// If we fall-out here, then every register in the group can be
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// renamed, as recorded in RenameMap.
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RenameOrder.erase(SuperRC);
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@ -704,13 +711,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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unsigned InsertPosIndex) {
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unsigned *KillIndices = State->GetKillIndices();
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unsigned *DefIndices = State->GetDefIndices();
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
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RegRefs = State->GetRegRefs();
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// The code below assumes that there is at least one instruction,
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// so just duck out immediately if the block is empty.
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if (SUnits.empty()) return 0;
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// For each regclass the next register to use for renaming.
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RenameOrderType RenameOrder;
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@ -729,17 +736,17 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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if (CriticalPathSet.any()) {
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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SUnit *SU = &SUnits[i];
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if (!CriticalPathSU ||
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((SU->getDepth() + SU->Latency) >
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if (!CriticalPathSU ||
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((SU->getDepth() + SU->Latency) >
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(CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
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CriticalPathSU = SU;
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}
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}
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CriticalPathMI = CriticalPathSU->getInstr();
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}
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#ifndef NDEBUG
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#ifndef NDEBUG
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DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
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DEBUG(dbgs() << "Available regs:");
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for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
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@ -766,7 +773,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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// Process the defs in MI...
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PrescanInstruction(MI, Count, PassthruRegs);
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// The dependence edges that represent anti- and output-
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// dependencies that are candidates for breaking.
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std::vector<SDep*> Edges;
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@ -779,7 +786,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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if (MI == CriticalPathMI) {
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CriticalPathSU = CriticalPathStep(CriticalPathSU);
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CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : 0;
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} else {
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} else {
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ExcludeRegs = &CriticalPathSet;
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}
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@ -790,14 +797,14 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
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SDep *Edge = Edges[i];
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SUnit *NextSU = Edge->getSUnit();
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if ((Edge->getKind() != SDep::Anti) &&
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(Edge->getKind() != SDep::Output)) continue;
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unsigned AntiDepReg = Edge->getReg();
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DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
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assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
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if (!AllocatableSet.test(AntiDepReg)) {
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// Don't break anti-dependencies on non-allocatable registers.
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DEBUG(dbgs() << " (non-allocatable)\n");
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@ -816,12 +823,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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} else {
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// No anti-dep breaking for implicit deps
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MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
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assert(AntiDepOp != NULL && "Can't find index for defined register operand");
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assert(AntiDepOp != NULL &&
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"Can't find index for defined register operand");
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if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) {
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DEBUG(dbgs() << " (implicit)\n");
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continue;
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}
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// If the SUnit has other dependencies on the SUnit that
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// it anti-depends on, don't bother breaking the
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// anti-dependency since those edges would prevent such
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@ -847,58 +855,59 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
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DEBUG(dbgs() << " (real dependency)\n");
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AntiDepReg = 0;
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break;
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} else if ((P->getSUnit() != NextSU) &&
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(P->getKind() == SDep::Data) &&
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} else if ((P->getSUnit() != NextSU) &&
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(P->getKind() == SDep::Data) &&
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(P->getReg() == AntiDepReg)) {
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DEBUG(dbgs() << " (other dependency)\n");
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AntiDepReg = 0;
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break;
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}
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}
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if (AntiDepReg == 0) continue;
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}
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assert(AntiDepReg != 0);
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if (AntiDepReg == 0) continue;
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// Determine AntiDepReg's register group.
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const unsigned GroupIndex = State->GetGroup(AntiDepReg);
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if (GroupIndex == 0) {
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DEBUG(dbgs() << " (zero group)\n");
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continue;
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}
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||||
|
||||
|
||||
DEBUG(dbgs() << '\n');
|
||||
|
||||
|
||||
// Look for a suitable register to use to break the anti-dependence.
|
||||
std::map<unsigned, unsigned> RenameMap;
|
||||
if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
|
||||
DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
|
||||
<< TRI->getName(AntiDepReg) << ":");
|
||||
|
||||
|
||||
// Handle each group register...
|
||||
for (std::map<unsigned, unsigned>::iterator
|
||||
S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
|
||||
unsigned CurrReg = S->first;
|
||||
unsigned NewReg = S->second;
|
||||
|
||||
DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
|
||||
TRI->getName(NewReg) << "(" <<
|
||||
|
||||
DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
|
||||
TRI->getName(NewReg) << "(" <<
|
||||
RegRefs.count(CurrReg) << " refs)");
|
||||
|
||||
|
||||
// Update the references to the old register CurrReg to
|
||||
// refer to the new register NewReg.
|
||||
std::pair<std::multimap<unsigned,
|
||||
AggressiveAntiDepState::RegisterReference>::iterator,
|
||||
std::pair<std::multimap<unsigned,
|
||||
AggressiveAntiDepState::RegisterReference>::iterator,
|
||||
std::multimap<unsigned,
|
||||
AggressiveAntiDepState::RegisterReference>::iterator>
|
||||
AggressiveAntiDepState::RegisterReference>::iterator>
|
||||
Range = RegRefs.equal_range(CurrReg);
|
||||
for (std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>::iterator
|
||||
for (std::multimap<unsigned,
|
||||
AggressiveAntiDepState::RegisterReference>::iterator
|
||||
Q = Range.first, QE = Range.second; Q != QE; ++Q) {
|
||||
Q->second.Operand->setReg(NewReg);
|
||||
}
|
||||
|
||||
|
||||
// We just went back in time and modified history; the
|
||||
// liveness information for CurrReg is now inconsistent. Set
|
||||
// the state as if it were dead.
|
||||
@ -906,7 +915,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
|
||||
RegRefs.erase(NewReg);
|
||||
DefIndices[NewReg] = DefIndices[CurrReg];
|
||||
KillIndices[NewReg] = KillIndices[CurrReg];
|
||||
|
||||
|
||||
State->UnionGroups(CurrReg, 0);
|
||||
RegRefs.erase(CurrReg);
|
||||
DefIndices[CurrReg] = KillIndices[CurrReg];
|
||||
@ -915,7 +924,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
|
||||
(DefIndices[CurrReg] == ~0u)) &&
|
||||
"Kill and Def maps aren't consistent for AntiDepReg!");
|
||||
}
|
||||
|
||||
|
||||
++Broken;
|
||||
DEBUG(dbgs() << '\n');
|
||||
}
|
||||
@ -924,6 +933,6 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
|
||||
|
||||
ScanInstruction(MI, Count);
|
||||
}
|
||||
|
||||
|
||||
return Broken;
|
||||
}
|
||||
|
||||
@ -30,7 +30,7 @@
|
||||
#include <map>
|
||||
|
||||
namespace llvm {
|
||||
/// Class AggressiveAntiDepState
|
||||
/// Class AggressiveAntiDepState
|
||||
/// Contains all the state necessary for anti-dep breaking.
|
||||
class AggressiveAntiDepState {
|
||||
public:
|
||||
@ -54,27 +54,27 @@ namespace llvm {
|
||||
/// is the parent of a group, or point to another node to indicate
|
||||
/// that it is a member of the same group as that node.
|
||||
std::vector<unsigned> GroupNodes;
|
||||
|
||||
|
||||
/// GroupNodeIndices - For each register, the index of the GroupNode
|
||||
/// currently representing the group that the register belongs to.
|
||||
/// Register 0 is always represented by the 0 group, a group
|
||||
/// composed of registers that are not eligible for anti-aliasing.
|
||||
unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister];
|
||||
|
||||
|
||||
/// RegRefs - Map registers to all their references within a live range.
|
||||
std::multimap<unsigned, RegisterReference> RegRefs;
|
||||
|
||||
|
||||
/// KillIndices - The index of the most recent kill (proceding bottom-up),
|
||||
/// or ~0u if the register is not live.
|
||||
unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
|
||||
|
||||
|
||||
/// DefIndices - The index of the most recent complete def (proceding bottom
|
||||
/// up), or ~0u if the register is live.
|
||||
unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
|
||||
|
||||
public:
|
||||
AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB);
|
||||
|
||||
|
||||
/// GetKillIndices - Return the kill indices.
|
||||
unsigned *GetKillIndices() { return KillIndices; }
|
||||
|
||||
@ -87,13 +87,14 @@ namespace llvm {
|
||||
// GetGroup - Get the group for a register. The returned value is
|
||||
// the index of the GroupNode representing the group.
|
||||
unsigned GetGroup(unsigned Reg);
|
||||
|
||||
|
||||
// GetGroupRegs - Return a vector of the registers belonging to a
|
||||
// group. If RegRefs is non-NULL then only included referenced registers.
|
||||
void GetGroupRegs(
|
||||
unsigned Group,
|
||||
std::vector<unsigned> &Regs,
|
||||
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs);
|
||||
std::multimap<unsigned,
|
||||
AggressiveAntiDepState::RegisterReference> *RegRefs);
|
||||
|
||||
// UnionGroups - Union Reg1's and Reg2's groups to form a new
|
||||
// group. Return the index of the GroupNode representing the
|
||||
@ -110,7 +111,7 @@ namespace llvm {
|
||||
};
|
||||
|
||||
|
||||
/// Class AggressiveAntiDepBreaker
|
||||
/// Class AggressiveAntiDepBreaker
|
||||
class AggressiveAntiDepBreaker : public AntiDepBreaker {
|
||||
MachineFunction& MF;
|
||||
MachineRegisterInfo &MRI;
|
||||
@ -130,14 +131,15 @@ namespace llvm {
|
||||
AggressiveAntiDepState *State;
|
||||
|
||||
public:
|
||||
AggressiveAntiDepBreaker(MachineFunction& MFi,
|
||||
AggressiveAntiDepBreaker(MachineFunction& MFi,
|
||||
TargetSubtarget::RegClassVector& CriticalPathRCs);
|
||||
~AggressiveAntiDepBreaker();
|
||||
|
||||
|
||||
/// Start - Initialize anti-dep breaking for a new basic block.
|
||||
void StartBlock(MachineBasicBlock *BB);
|
||||
|
||||
/// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
|
||||
/// BreakAntiDependencies - Identifiy anti-dependencies along the critical
|
||||
/// path
|
||||
/// of the ScheduleDAG and break them by renaming registers.
|
||||
///
|
||||
unsigned BreakAntiDependencies(std::vector<SUnit>& SUnits,
|
||||
@ -160,7 +162,7 @@ namespace llvm {
|
||||
/// IsImplicitDefUse - Return true if MO represents a register
|
||||
/// that is both implicitly used and defined in MI
|
||||
bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO);
|
||||
|
||||
|
||||
/// GetPassthruRegs - If MI implicitly def/uses a register, then
|
||||
/// return that register and all subregisters.
|
||||
void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
|
||||
|
||||
@ -290,7 +290,8 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
|
||||
unsigned
|
||||
CriticalAntiDepBreaker::findSuitableFreeRegister(unsigned AntiDepReg,
|
||||
unsigned LastNewReg,
|
||||
const TargetRegisterClass *RC) {
|
||||
const TargetRegisterClass *RC)
|
||||
{
|
||||
for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
|
||||
RE = RC->allocation_order_end(MF); R != RE; ++R) {
|
||||
unsigned NewReg = *R;
|
||||
@ -302,10 +303,10 @@ CriticalAntiDepBreaker::findSuitableFreeRegister(unsigned AntiDepReg,
|
||||
if (NewReg == LastNewReg) continue;
|
||||
// If NewReg is dead and NewReg's most recent def is not before
|
||||
// AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
|
||||
assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) &&
|
||||
"Kill and Def maps aren't consistent for AntiDepReg!");
|
||||
assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) &&
|
||||
"Kill and Def maps aren't consistent for NewReg!");
|
||||
assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))
|
||||
&& "Kill and Def maps aren't consistent for AntiDepReg!");
|
||||
assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
|
||||
&& "Kill and Def maps aren't consistent for NewReg!");
|
||||
if (KillIndices[NewReg] != ~0u ||
|
||||
Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
|
||||
KillIndices[AntiDepReg] > DefIndices[NewReg])
|
||||
|
||||
@ -64,11 +64,12 @@ namespace llvm {
|
||||
public:
|
||||
CriticalAntiDepBreaker(MachineFunction& MFi);
|
||||
~CriticalAntiDepBreaker();
|
||||
|
||||
|
||||
/// Start - Initialize anti-dep breaking for a new basic block.
|
||||
void StartBlock(MachineBasicBlock *BB);
|
||||
|
||||
/// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
|
||||
/// BreakAntiDependencies - Identifiy anti-dependencies along the critical
|
||||
/// path
|
||||
/// of the ScheduleDAG and break them by renaming registers.
|
||||
///
|
||||
unsigned BreakAntiDependencies(std::vector<SUnit>& SUnits,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user