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If the false case is the current basic block, then this is a self loop.
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -562,6 +562,15 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
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} else {
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std::vector<SDOperand> Ops;
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Ops.push_back(getRoot());
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// If the false case is the current basic block, then this is a self
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// loop. We do not want to emit "Loop: ... brcond Out; br Loop", as it
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// adds an extra instruction in the loop. Instead, invert the
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// condition and emit "Loop: ... br!cond Loop; br Out.
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if (CurMBB == Succ1MBB) {
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std::swap(Succ0MBB, Succ1MBB);
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SDOperand True = DAG.getConstant(1, Cond.getValueType());
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Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
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}
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Ops.push_back(Cond);
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Ops.push_back(DAG.getBasicBlock(Succ0MBB));
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Ops.push_back(DAG.getBasicBlock(Succ1MBB));
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@ -1046,17 +1046,6 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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if (N->getOpcode() == ISD::BRTWOWAY_CC) {
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SDOperand CondTrueBlock = N->getOperand(4);
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SDOperand CondFalseBlock = N->getOperand(5);
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// If the false case is the current basic block, then this is a self loop.
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// We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an
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// extra dispatch group to the loop. Instead, invert the condition and
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// emit "Loop: ... br!cond Loop; br Out
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if (cast<BasicBlockSDNode>(CondFalseBlock)->getBasicBlock() == BB) {
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std::swap(CondTrueBlock, CondFalseBlock);
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CC = getSetCCInverse(CC,
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MVT::isInteger(N->getOperand(2).getValueType()));
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}
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unsigned Opc = getBCCForSetCC(CC);
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SDOperand CB =
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SDOperand(CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
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