From 2997985b4cafc2a1e562819a2f3e0c6abe5fb223 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 17 May 2010 20:01:22 +0000 Subject: [PATCH] Remove debug option. Add comment on spill order determinism. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103961 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocFast.cpp | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index a8d1e0d1f08..3270b562026 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -35,9 +35,6 @@ #include using namespace llvm; -static cl::opt VerifyFastRegalloc("verify-fast-regalloc", cl::Hidden, - cl::desc("Verify machine code before fast regalloc")); - STATISTIC(NumStores, "Number of stores added"); STATISTIC(NumLoads , "Number of loads added"); STATISTIC(NumCopies, "Number of copies coalesced"); @@ -269,8 +266,10 @@ void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, void RAFast::spillAll(MachineInstr *MI) { if (LiveVirtRegs.empty()) return; isBulkSpilling = true; - for (LiveRegMap::iterator i = LiveVirtRegs.begin(), - e = LiveVirtRegs.end(); i != e; ++i) + // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order + // of spilling here is deterministic, if arbitrary. + for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end(); + i != e; ++i) spillVirtReg(MI, i); LiveVirtRegs.clear(); isBulkSpilling = false; @@ -796,8 +795,6 @@ bool RAFast::runOnMachineFunction(MachineFunction &Fn) { DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n" << "********** Function: " << ((Value*)Fn.getFunction())->getName() << '\n'); - if (VerifyFastRegalloc) - Fn.verify(this, true); MF = &Fn; MRI = &MF->getRegInfo(); TM = &Fn.getTarget();