mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-07 14:33:15 +00:00
Two changes:
* In promote32, if we can just promote a constant value, do so instead of promoting a constant dynamically. * In visitReturn inst, actually USE the promote32 argument that takes a Value* The end result of this is that we now generate this: test: mov %EAX, 0 ret instead of... test: mov %AX, 0 movzx %EAX, %AX ret for: ushort %test() { ret ushort 0 } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12679 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1107,10 +1107,18 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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bool isUnsigned = VR.Ty->isUnsigned();
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bool isUnsigned = VR.Ty->isUnsigned();
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// Make sure we have the register number for this value...
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Value *Val = VR.Val;
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unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
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const Type *Ty = VR.Ty;
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if (Val)
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if (Constant *C = dyn_cast<Constant>(Val)) {
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Val = ConstantExpr::getCast(C, Type::IntTy);
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Ty = Type::IntTy;
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}
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switch (getClassB(VR.Ty)) {
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// Make sure we have the register number for this value...
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unsigned Reg = Val ? getReg(Val) : VR.Reg;
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switch (getClassB(Ty)) {
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case cByte:
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case cByte:
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// Extend value into target register (8->32)
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// Extend value into target register (8->32)
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if (isUnsigned)
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if (isUnsigned)
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@ -1152,27 +1160,30 @@ void ISel::visitReturnInst(ReturnInst &I) {
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}
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}
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Value *RetVal = I.getOperand(0);
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Value *RetVal = I.getOperand(0);
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unsigned RetReg = getReg(RetVal);
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switch (getClassB(RetVal->getType())) {
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switch (getClassB(RetVal->getType())) {
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case cByte: // integral return values: extend or move into EAX and return
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case cByte: // integral return values: extend or move into EAX and return
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case cShort:
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case cShort:
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case cInt:
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case cInt:
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promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
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promote32(X86::EAX, ValueRecord(RetVal));
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// Declare that EAX is live on exit
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// Declare that EAX is live on exit
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BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
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BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
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break;
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break;
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case cFP: // Floats & Doubles: Return in ST(0)
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case cFP: { // Floats & Doubles: Return in ST(0)
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unsigned RetReg = getReg(RetVal);
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BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
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BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
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// Declare that top-of-stack is live on exit
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// Declare that top-of-stack is live on exit
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BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
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BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
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break;
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break;
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case cLong:
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}
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case cLong: {
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unsigned RetReg = getReg(RetVal);
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
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BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
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BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
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// Declare that EAX & EDX are live on exit
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// Declare that EAX & EDX are live on exit
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BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
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BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
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.addReg(X86::ESP);
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.addReg(X86::ESP);
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break;
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break;
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}
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default:
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default:
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visitInstruction(I);
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visitInstruction(I);
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}
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}
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@ -1107,10 +1107,18 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
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void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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bool isUnsigned = VR.Ty->isUnsigned();
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bool isUnsigned = VR.Ty->isUnsigned();
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// Make sure we have the register number for this value...
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Value *Val = VR.Val;
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unsigned Reg = VR.Val ? getReg(VR.Val) : VR.Reg;
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const Type *Ty = VR.Ty;
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if (Val)
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if (Constant *C = dyn_cast<Constant>(Val)) {
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Val = ConstantExpr::getCast(C, Type::IntTy);
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Ty = Type::IntTy;
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}
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switch (getClassB(VR.Ty)) {
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// Make sure we have the register number for this value...
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unsigned Reg = Val ? getReg(Val) : VR.Reg;
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switch (getClassB(Ty)) {
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case cByte:
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case cByte:
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// Extend value into target register (8->32)
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// Extend value into target register (8->32)
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if (isUnsigned)
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if (isUnsigned)
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@ -1152,27 +1160,30 @@ void ISel::visitReturnInst(ReturnInst &I) {
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}
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}
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Value *RetVal = I.getOperand(0);
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Value *RetVal = I.getOperand(0);
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unsigned RetReg = getReg(RetVal);
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switch (getClassB(RetVal->getType())) {
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switch (getClassB(RetVal->getType())) {
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case cByte: // integral return values: extend or move into EAX and return
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case cByte: // integral return values: extend or move into EAX and return
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case cShort:
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case cShort:
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case cInt:
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case cInt:
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promote32(X86::EAX, ValueRecord(RetReg, RetVal->getType()));
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promote32(X86::EAX, ValueRecord(RetVal));
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// Declare that EAX is live on exit
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// Declare that EAX is live on exit
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BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
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BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
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break;
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break;
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case cFP: // Floats & Doubles: Return in ST(0)
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case cFP: { // Floats & Doubles: Return in ST(0)
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unsigned RetReg = getReg(RetVal);
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BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
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BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
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// Declare that top-of-stack is live on exit
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// Declare that top-of-stack is live on exit
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BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
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BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
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break;
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break;
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case cLong:
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}
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case cLong: {
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unsigned RetReg = getReg(RetVal);
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
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BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
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BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
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BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
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// Declare that EAX & EDX are live on exit
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// Declare that EAX & EDX are live on exit
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BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
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BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
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.addReg(X86::ESP);
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.addReg(X86::ESP);
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break;
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break;
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}
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default:
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default:
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visitInstruction(I);
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visitInstruction(I);
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}
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}
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