From 29d525a3edf6df1e7797ecb60ebfa445a27e37c6 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Mon, 7 Nov 2011 21:35:45 +0000 Subject: [PATCH] Add code needed for copying between 64-bit integer and floating pointer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144017 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstrInfo.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 559943a8dba..5358dc00c10 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -131,6 +131,8 @@ copyPhysReg(MachineBasicBlock &MBB, Opc = Mips::FMOV_S; else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) Opc = Mips::FMOV_D32; + else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) + Opc = Mips::FMOV_D64; else if (Mips::CCRRegClass.contains(DestReg, SrcReg)) Opc = Mips::MOVCCRToCCR; else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg. @@ -140,12 +142,16 @@ copyPhysReg(MachineBasicBlock &MBB, Opc = Mips::MFHI64, SrcReg = 0; else if (SrcReg == Mips::LO64) Opc = Mips::MFLO64, SrcReg = 0; + else if (Mips::FGR64RegClass.contains(SrcReg)) + Opc = Mips::DMFC1; } else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg. if (DestReg == Mips::HI64) Opc = Mips::MTHI64, DestReg = 0; else if (DestReg == Mips::LO64) Opc = Mips::MTLO64, DestReg = 0; + else if (Mips::FGR64RegClass.contains(DestReg)) + Opc = Mips::DMTC1; } assert(Opc && "Cannot copy registers");