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R600/SI: Use v_madmk_f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230149 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
c490f78e53
commit
29f97a6c46
@ -892,10 +892,57 @@ bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1);
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MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2);
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// The VOP2 src0 can't be an SGPR since the constant bus use will be the
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// literal constant.
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if (Src0->isReg() && RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))
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return false;
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// Multiplied part is the constant: Use v_madmk_f32
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// We should only expect these to be on src0 due to canonicalizations.
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if (Src0->isReg() && Src0->getReg() == Reg) {
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if (!Src1->isReg() ||
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(Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
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return false;
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if (!Src2->isReg() ||
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(Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))))
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return false;
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// We need to do some weird looking operand shuffling since the madmk
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// operands are out of the normal expected order with the multiplied
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// constant as the last operand.
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//
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// v_mad_f32 src0, src1, src2 -> v_madmk_f32 src0 * src2K + src1
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// src0 -> src2 K
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// src1 -> src0
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// src2 -> src1
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const int64_t Imm = DefMI->getOperand(1).getImm();
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// FIXME: This would be a lot easier if we could return a new instruction
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// instead of having to modify in place.
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// Remove these first since they are at the end.
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UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(AMDGPU::V_MAD_F32,
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AMDGPU::OpName::omod));
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UseMI->RemoveOperand(AMDGPU::getNamedOperandIdx(AMDGPU::V_MAD_F32,
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AMDGPU::OpName::clamp));
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unsigned Src1Reg = Src1->getReg();
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unsigned Src1SubReg = Src1->getSubReg();
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unsigned Src2Reg = Src2->getReg();
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unsigned Src2SubReg = Src2->getSubReg();
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Src0->setReg(Src1Reg);
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Src0->setSubReg(Src1SubReg);
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Src1->setReg(Src2Reg);
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Src1->setSubReg(Src2SubReg);
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Src2->ChangeToImmediate(Imm);
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removeModOperands(*UseMI);
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UseMI->setDesc(get(AMDGPU::V_MADMK_F32));
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bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
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if (DeleteDef)
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DefMI->eraseFromParent();
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return true;
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}
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// Added part is the constant: Use v_madak_f32
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if (Src2->isReg() && Src2->getReg() == Reg) {
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181
test/CodeGen/R600/madmk.ll
Normal file
181
test/CodeGen/R600/madmk.ll
Normal file
@ -0,0 +1,181 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare float @llvm.fabs.f32(float) nounwind readnone
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; GCN-LABEL: {{^}}madmk_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN: v_madmk_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
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define void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.0, align 4
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%b = load float addrspace(1)* %gep.1, align 4
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}madmk_2_use_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
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; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VK]], [[VB]]
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; GCN-DAG: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VK]], [[VC]]
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; GCN: s_endpgm
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define void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%in.gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%in.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
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%in.gep.2 = getelementptr float addrspace(1)* %in.gep.0, i32 2
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%out.gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%out.gep.1 = getelementptr float addrspace(1)* %in.gep.0, i32 1
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%a = load float addrspace(1)* %in.gep.0, align 4
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%b = load float addrspace(1)* %in.gep.1, align 4
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%c = load float addrspace(1)* %in.gep.2, align 4
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%mul0 = fmul float %a, 10.0
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%mul1 = fmul float %a, 10.0
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%madmk0 = fadd float %mul0, %b
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%madmk1 = fadd float %mul1, %c
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store float %madmk0, float addrspace(1)* %out.gep.0, align 4
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store float %madmk1, float addrspace(1)* %out.gep.1, align 4
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ret void
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}
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; We don't get any benefit if the constant is an inline immediate.
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; GCN-LABEL: {{^}}madmk_inline_imm_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN: v_mad_f32 {{v[0-9]+}}, 4.0, [[VA]], [[VB]]
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define void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.0, align 4
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%b = load float addrspace(1)* %gep.1, align 4
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%mul = fmul float %a, 4.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_s_madmk_f32:
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; GCN-NOT: v_madmk_f32
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; GCN: v_mad_f32
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; GCN: s_endpgm
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define void @s_s_madmk_f32(float addrspace(1)* noalias %out, float %a, float %b) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_s_madmk_f32:
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; GCN-NOT: v_madmk_f32
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; GCN: v_mad_f32
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; GCN: s_endpgm
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define void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.0, align 4
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}scalar_vector_madmk_f32:
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; GCN-NOT: v_madmk_f32
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; GCN: v_mad_f32
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; GCN: s_endpgm
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define void @scalar_vector_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %a) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%b = load float addrspace(1)* %gep.0, align 4
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}}
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define void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.0, align 4
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%b = load float addrspace(1)* %gep.1, align 4
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%a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
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%mul = fmul float %a.fabs, 10.0
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%madmk = fadd float %mul, %b
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32:
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; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, |{{[sv][0-9]+}}|
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define void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.0, align 4
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%b = load float addrspace(1)* %gep.1, align 4
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%b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, %b.fabs
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}madmk_add_inline_imm_f32:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
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; GCN: v_mad_f32 {{v[0-9]+}}, [[VK]], [[A]], 2.0
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define void @madmk_add_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
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%tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.0, align 4
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%mul = fmul float %a, 10.0
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%madmk = fadd float %mul, 2.0
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store float %madmk, float addrspace(1)* %out.gep, align 4
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ret void
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}
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@ -50,7 +50,7 @@ define void @uint_to_fp_v4i32_to_v4f32(<4 x float> addrspace(1)* %out, <4 x i32>
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; R600: MULADD_IEEE
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; SI: v_cvt_f32_u32_e32
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; SI: v_cvt_f32_u32_e32
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; SI: v_mad_f32
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; SI: v_madmk_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4f800000
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; SI: s_endpgm
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define void @uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) {
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entry:
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