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now that generic vector types aren't selected onto MMX operations,

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we don't need -disable-mmx anymore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122189 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-12-19 20:19:20 +00:00
parent 6f948be128
commit 2a786eb030
1 changed files with 4 additions and 8 deletions
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12
lib/Target/X86/X86ISelLowering.cpp
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@ -55,9 +55,6 @@ using namespace dwarf;
STATISTIC(NumTailCalls, "Number of tail calls"); STATISTIC(NumTailCalls, "Number of tail calls");
static cl::opt<bool>
DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
// Forward declarations. // Forward declarations.
static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
SDValue V2); SDValue V2);
@ -613,7 +610,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// FIXME: In order to prevent SSE instructions being expanded to MMX ones // FIXME: In order to prevent SSE instructions being expanded to MMX ones
// with -msoft-float, disable use of MMX as well. // with -msoft-float, disable use of MMX as well.
if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { if (!UseSoftFloat && Subtarget->hasMMX()) {
addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
// No operations on x86mmx supported, everything uses intrinsics. // No operations on x86mmx supported, everything uses intrinsics.
} }
@ -8604,9 +8601,8 @@ SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
EVT SrcVT = Op.getOperand(0).getValueType(); EVT SrcVT = Op.getOperand(0).getValueType();
EVT DstVT = Op.getValueType(); EVT DstVT = Op.getValueType();
assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() && assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
Subtarget->hasMMX() && !DisableMMX) && Subtarget->hasMMX() && "Unexpected custom BITCAST");
"Unexpected custom BITCAST");
assert((DstVT == MVT::i64 || assert((DstVT == MVT::i64 ||
(DstVT.isVector() && DstVT.getSizeInBits()==64)) && (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
"Unexpected custom BITCAST"); "Unexpected custom BITCAST");
@ -11793,7 +11789,7 @@ TargetLowering::ConstraintWeight
weight = CW_SpecificReg; weight = CW_SpecificReg;
break; break;
case 'y': case 'y':
if (type->isX86_MMXTy() && !DisableMMX && Subtarget->hasMMX()) if (type->isX86_MMXTy() && Subtarget->hasMMX())
weight = CW_SpecificReg; weight = CW_SpecificReg;
break; break;
case 'x': case 'x':