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Use MRegisterInfo, if available, to print symbolic register names

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4438 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-10-30 00:58:19 +00:00
parent e5f5221b5e
commit 2a79a0927c
1 changed files with 14 additions and 7 deletions
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21
lib/CodeGen/MachineInstr.cpp
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@ -7,6 +7,7 @@
#include "llvm/Value.h" #include "llvm/Value.h"
#include "llvm/Target/MachineInstrInfo.h" // FIXME: shouldn't need this! #include "llvm/Target/MachineInstrInfo.h" // FIXME: shouldn't need this!
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
using std::cerr; using std::cerr;
// Global variable holding an array of descriptors for machine instructions. // Global variable holding an array of descriptors for machine instructions.
@ -191,14 +192,20 @@ OutputValue(std::ostream &os, const Value* val)
return os << (void*) val << ")"; // print address only return os << (void*) val << ")"; // print address only
} }
static inline std::ostream& static inline void OutputReg(std::ostream &os, unsigned RegNo,
OutputReg(std::ostream &os, unsigned int regNum) const MRegisterInfo *MRI = 0) {
{ if (MRI) {
return os << "%mreg(" << regNum << ")"; if (RegNo < MRegisterInfo::FirstVirtualRegister)
os << "%" << MRI->get(RegNo).Name;
else
os << "%reg" << RegNo;
} else
os << "%mreg(" << RegNo << ")";
} }
static void print(const MachineOperand &MO, std::ostream &OS, static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine &TM) { const TargetMachine &TM) {
const MRegisterInfo *MRI = TM.getRegisterInfo();
bool CloseParen = true; bool CloseParen = true;
if (MO.opHiBits32()) if (MO.opHiBits32())
OS << "%lm("; OS << "%lm(";
@ -220,18 +227,18 @@ static void print(const MachineOperand &MO, std::ostream &OS,
OS << "=="; OS << "==";
} }
if (MO.hasAllocatedReg()) if (MO.hasAllocatedReg())
OutputReg(OS, MO.getAllocatedRegNum()); OutputReg(OS, MO.getAllocatedRegNum(), MRI);
break; break;
case MachineOperand::MO_CCRegister: case MachineOperand::MO_CCRegister:
OS << "%ccreg"; OS << "%ccreg";
OutputValue(OS, MO.getVRegValue()); OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) { if (MO.hasAllocatedReg()) {
OS << "=="; OS << "==";
OutputReg(OS, MO.getAllocatedRegNum()); OutputReg(OS, MO.getAllocatedRegNum(), MRI);
} }
break; break;
case MachineOperand::MO_MachineRegister: case MachineOperand::MO_MachineRegister:
OutputReg(OS, MO.getMachineRegNum()); OutputReg(OS, MO.getMachineRegNum(), MRI);
break; break;
case MachineOperand::MO_SignExtendedImmed: case MachineOperand::MO_SignExtendedImmed:
OS << (long)MO.getImmedValue(); OS << (long)MO.getImmedValue();