mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-05 14:34:55 +00:00
R600/SI: Only select SALU instructions in the entry or exit block
SALU instructions ignore control flow, so it is not always safe to use them within branches. This is a partial solution to this problem until we can come up with something better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207590 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
19a970b2da
commit
2a90e446c0
@ -16,9 +16,11 @@
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#include "AMDGPURegisterInfo.h"
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#include "R600InstrInfo.h"
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#include "SIISelLowering.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Function.h"
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using namespace llvm;
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@ -70,6 +72,11 @@ private:
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bool isLocalLoad(const LoadSDNode *N) const;
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bool isRegionLoad(const LoadSDNode *N) const;
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/// \returns True if the current basic block being selected is at control
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/// flow depth 0. Meaning that the current block dominates the
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// exit block.
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bool isCFDepth0() const;
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const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
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bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
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bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
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@ -565,6 +572,14 @@ bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
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return false;
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}
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bool AMDGPUDAGToDAGISel::isCFDepth0() const {
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// FIXME: Figure out a way to use DominatorTree analysis here.
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const BasicBlock *CurBlock = FuncInfo->MBB->getBasicBlock();
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const Function *Fn = FuncInfo->Fn;
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return &Fn->front() == CurBlock || &Fn->back() == CurBlock;
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}
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const char *AMDGPUDAGToDAGISel::getPassName() const {
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return "AMDGPU DAG->DAG Pattern Instruction Selection";
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}
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@ -32,14 +32,16 @@ def isSI : Predicate<"Subtarget.getGeneration() "
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def isCI : Predicate<"Subtarget.getGeneration() "
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">= AMDGPUSubtarget::SEA_ISLANDS">;
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def WAIT_FLAG : InstFlag<"printWaitFlag">;
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def isCFDepth0 : Predicate<"isCFDepth0()">;
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let Predicates = [isSI] in {
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def WAIT_FLAG : InstFlag<"printWaitFlag">;
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//===----------------------------------------------------------------------===//
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// SMRD Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isSI, isCFDepth0] in {
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let mayLoad = 1 in {
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// We are using the SGPR_32 and not the SReg_32 register class for 32-bit
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@ -76,10 +78,14 @@ defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
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//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
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//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
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} // let Predicates = [isSI, isCFDepth0]
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//===----------------------------------------------------------------------===//
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// SOP1 Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isSI, isCFDepth0] in {
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let neverHasSideEffects = 1 in {
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let isMoveImm = 1 in {
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@ -152,10 +158,14 @@ def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
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def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
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def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
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} // let Predicates = [isSI, isCFDepth0]
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//===----------------------------------------------------------------------===//
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// SOP2 Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isSI, isCFDepth0] in {
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let Defs = [SCC] in { // Carry out goes to SCC
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let isCommutable = 1 in {
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def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
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@ -209,11 +219,6 @@ def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
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[(set i64:$dst, (and i64:$src0, i64:$src1))]
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>;
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def : Pat <
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(i1 (and i1:$src0, i1:$src1)),
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(S_AND_B64 $src0, $src1)
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>;
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def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
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[(set i32:$dst, (or i32:$src0, i32:$src1))]
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>;
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@ -222,17 +227,12 @@ def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
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[(set i64:$dst, (or i64:$src0, i64:$src1))]
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>;
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def : Pat <
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(i1 (or i1:$src0, i1:$src1)),
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(S_OR_B64 $src0, $src1)
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>;
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def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
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[(set i32:$dst, (xor i32:$src0, i32:$src1))]
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>;
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def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
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[(set i1:$dst, (xor i1:$src0, i1:$src1))]
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[(set i64:$dst, (xor i64:$src0, i64:$src1))]
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>;
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def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
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def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
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@ -279,10 +279,14 @@ def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
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//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
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def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
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} // let Predicates = [isSI, isCFDepth0]
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//===----------------------------------------------------------------------===//
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// SOPC Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isSI, isCFDepth0] in {
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def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
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def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
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def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
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@ -301,10 +305,14 @@ def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
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////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
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//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
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} // let Predicates = [isSI, isCFDepth0]
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//===----------------------------------------------------------------------===//
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// SOPK Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isSI, isCFDepth0] in {
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def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
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def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
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@ -353,10 +361,14 @@ def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
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//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
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//def EXP : EXP_ <0x00000000, "EXP", []>;
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} // let Predicates = [isSI, isCFDepth0]
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//===----------------------------------------------------------------------===//
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// SOPP Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isSI] in {
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//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
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let isTerminator = 1 in {
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@ -449,6 +461,10 @@ let Uses = [EXEC] in {
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//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
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} // End hasSideEffects
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} // let Predicates = [isSI, isCFDepth0]
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let Predicates = [isSI] in {
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//===----------------------------------------------------------------------===//
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// VOPC Instructions
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//===----------------------------------------------------------------------===//
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@ -1173,27 +1189,43 @@ defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32",
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defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>;
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defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>;
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defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>;
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defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>;
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defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>;
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defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>;
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defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32",
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[(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>;
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defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32",
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[(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>;
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defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32",
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[(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>;
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defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32",
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[(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>;
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defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32",
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[(set i32:$dst, (srl i32:$src0, i32:$src1))]
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>;
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defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>;
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defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">;
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defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>;
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defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32",
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[(set i32:$dst, (sra i32:$src0, i32:$src1))]
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>;
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defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">;
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let hasPostISelHook = 1 in {
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defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", []>;
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defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32",
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[(set i32:$dst, (shl i32:$src0, i32:$src1))]
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>;
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}
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defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">;
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defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", []>;
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defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", []>;
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defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", []>;
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defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32",
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[(set i32:$dst, (and i32:$src0, i32:$src1))]>;
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defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32",
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[(set i32:$dst, (or i32:$src0, i32:$src1))]
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>;
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defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32",
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[(set i32:$dst, (xor i32:$src0, i32:$src1))]
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>;
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} // End isCommutable = 1
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@ -1209,14 +1241,18 @@ defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
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let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
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// No patterns so that the scalar instructions are always selected.
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// The scalar versions will be replaced with vector when needed later.
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defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>;
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defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>;
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defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
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[(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>;
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defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
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[(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>;
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defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32,
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"V_SUB_I32">;
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let Uses = [VCC] in { // Carry-in comes from VCC
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defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>;
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defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>;
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defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32",
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[(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>;
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defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32",
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[(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>;
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defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32,
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"V_SUBB_U32">;
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} // End Uses = [VCC]
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@ -1592,6 +1628,45 @@ def : Pat <
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(S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
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>;
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//===----------------------------------------------------------------------===//
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// SOP2 Patterns
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//===----------------------------------------------------------------------===//
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def : Pat <
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(i1 (and i1:$src0, i1:$src1)),
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(S_AND_B64 $src0, $src1)
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>;
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def : Pat <
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(i1 (or i1:$src0, i1:$src1)),
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(S_OR_B64 $src0, $src1)
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>;
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def : Pat <
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(i1 (xor i1:$src0, i1:$src1)),
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(S_XOR_B64 $src0, $src1)
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>;
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//===----------------------------------------------------------------------===//
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// VOP2 Patterns
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//===----------------------------------------------------------------------===//
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def : Pat <
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(or i64:$src0, i64:$src1),
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(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0),
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(EXTRACT_SUBREG i64:$src1, sub0)), sub0),
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(V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1),
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(EXTRACT_SUBREG i64:$src1, sub1)), sub1)
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>;
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class SextInReg <ValueType vt, int ShiftAmt> : Pat <
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(sext_inreg i32:$src0, vt),
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(V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0))
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>;
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def : SextInReg <i8, 24>;
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def : SextInReg <i16, 16>;
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/********** ======================= **********/
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/********** Image sampling patterns **********/
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27
test/CodeGen/R600/sgpr-control-flow.ll
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27
test/CodeGen/R600/sgpr-control-flow.ll
Normal file
@ -0,0 +1,27 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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;
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;
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; Most SALU instructions ignore control flow, so we need to make sure
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; they don't overwrite values from other blocks.
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; SI-NOT: S_ADD
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define void @sgpr_if_else(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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entry:
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%0 = icmp eq i32 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = add i32 %b, %c
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br label %endif
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else:
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%2 = add i32 %d, %e
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br label %endif
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endif:
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%3 = phi i32 [%1, %if], [%2, %else]
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%4 = add i32 %3, %a
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store i32 %4, i32 addrspace(1)* %out
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ret void
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}
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