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Add MC support for the v8fp instructions: vmaxnm and vminnm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185767 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1549,7 +1549,7 @@ class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
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}
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// FP, binary, not predicated
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class ADbInp<bits<5> opcod1, bits<2> opcod2, dag oops, dag iops,
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class ADbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
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InstrItinClass itin, string asm, list<dag> pattern>
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: VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
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VFPBinaryFrm, itin, asm, "", pattern>
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@@ -1573,7 +1573,7 @@ class ADbInp<bits<5> opcod1, bits<2> opcod2, dag oops, dag iops,
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let Inst{21-20} = opcod2;
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let Inst{11-9} = 0b101;
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let Inst{8} = 1; // double precision
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let Inst{6} = 0;
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let Inst{6} = opcod3;
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let Inst{4} = 0;
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}
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@@ -1637,7 +1637,7 @@ class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
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}
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// Single precision, binary, not predicated
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class ASbInp<bits<5> opcod1, bits<2> opcod2, dag oops, dag iops,
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class ASbInp<bits<5> opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
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InstrItinClass itin, string asm, list<dag> pattern>
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: VFPXI<oops, iops, AddrModeNone, 4, IndexModeNone,
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VFPBinaryFrm, itin, asm, "", pattern>
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@@ -1661,7 +1661,7 @@ class ASbInp<bits<5> opcod1, bits<2> opcod2, dag oops, dag iops,
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let Inst{21-20} = opcod2;
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let Inst{11-9} = 0b101;
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let Inst{8} = 0; // Single precision
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let Inst{6} = 0;
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let Inst{6} = opcod3;
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let Inst{4} = 0;
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}
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@@ -335,12 +335,12 @@ def VNMULS : ASbI<0b11100, 0b10, 1, 0,
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multiclass vsel_inst<string op, bits<2> opc> {
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let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
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def S : ASbInp<0b11100, opc,
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def S : ASbInp<0b11100, opc, 0,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
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[]>, Requires<[HasV8FP]>;
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def D : ADbInp<0b11100, opc,
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def D : ADbInp<0b11100, opc, 0,
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(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
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NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
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[]>, Requires<[HasV8FP]>;
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@@ -352,6 +352,23 @@ defm VSELGE : vsel_inst<"ge", 0b10>;
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defm VSELEQ : vsel_inst<"eq", 0b00>;
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defm VSELVS : vsel_inst<"vs", 0b01>;
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multiclass vmaxmin_inst<string op, bit opc> {
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let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
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def S : ASbInp<0b11101, 0b00, opc,
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(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
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NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
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[]>, Requires<[HasV8FP]>;
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def D : ADbInp<0b11101, 0b00, opc,
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(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
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NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
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[]>, Requires<[HasV8FP]>;
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}
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}
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defm VMAXNM : vmaxmin_inst<"vmaxnm", 0>;
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defm VMINNM : vmaxmin_inst<"vminnm", 1>;
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// Match reassociated forms only if not sign dependent rounding.
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def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
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(VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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@@ -4905,7 +4905,8 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
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Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
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Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
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Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
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Mnemonic == "fmuls" || Mnemonic.startswith("vsel"))
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Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
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Mnemonic.startswith("vsel"))
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return Mnemonic;
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// First, split out any predication code. Ignore mnemonics we know aren't
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@@ -5005,7 +5006,8 @@ getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
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Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
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Mnemonic == "trap" || Mnemonic == "setend" ||
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Mnemonic.startswith("cps") || Mnemonic.startswith("vsel")) {
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Mnemonic.startswith("cps") || Mnemonic == "vmaxnm" ||
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Mnemonic == "vminnm" || Mnemonic.startswith("vsel")) {
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// These mnemonics are never predicable
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CanAcceptPredicationCode = false;
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} else if (!isThumb()) {
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