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The r128103 fix to cope with the removal of addressing modes from the MC instructions

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were incomplete.  The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-24 00:28:38 +00:00
parent 5ffe37f2c7
commit 2abc9d2444
2 changed files with 10 additions and 2 deletions
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9
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -1806,7 +1806,7 @@ static bool DisassembleVFPLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
assert(NumOps >= 5 && "VFPLdStMulFrm expects NumOps >= 5");
assert(NumOps >= 4 && "VFPLdStMulFrm expects NumOps >= 4");
unsigned &OpIdx = NumOpsAdded;
@ -1830,7 +1830,7 @@ static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
OpIdx += 4;
OpIdx += 3;
bool isSPVFP = (Opcode == ARM::VLDMSIA || Opcode == ARM::VLDMSDB ||
Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMSDB_UPD ||
@ -1844,6 +1844,11 @@ static bool DisassembleVFPLdStMulFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// Fill the variadic part of reglist.
unsigned char Imm8 = insn & 0xFF;
unsigned Regs = isSPVFP ? Imm8 : Imm8/2;
// Apply some sanity checks before proceeding.
if (Regs == 0 || (RegD + Regs) > 32 || (!isSPVFP && Regs > 16))
return false;
for (unsigned i = 0; i < Regs; ++i) {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID,
RegD + i)));

3
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -169,3 +169,6 @@
# CHECK: vcmpe.f64 d8, #0
0xc0 0x8b 0xb5 0xee
# CHECK: vldmdb r2, {s7, s8, s9, s10, s11}
0x05 0x3a 0x52 0xed