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Ensure that zero vectors are always v4i32, which forces them to CSE with

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each other.  This implements CodeGen/PowerPC/vxor-canonicalize.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27609 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-04-12 16:53:28 +00:00
parent 8e7401e52f
commit 2b1c3258d6
2 changed files with 13 additions and 8 deletions
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14
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -923,11 +923,19 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::BUILD_VECTOR:
// If this is a case we can't handle, return null and let the default
// expansion code take care of it. If we CAN select this case, return Op.
// See if this is all zeros.
// FIXME: We should handle splat(-0.0), and other cases here.
if (ISD::isBuildVectorAllZeros(Op.Val))
// See if this is all zeros.
if (ISD::isBuildVectorAllZeros(Op.Val)) {
// Canonicalize all zero vectors to be v4i32.
if (Op.getValueType() != MVT::v4i32) {
SDOperand Z = DAG.getConstant(0, MVT::i32);
Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
}
return Op;
}
if (PPC::get_VSPLI_elt(Op.Val, 1, DAG).Val || // vspltisb
PPC::get_VSPLI_elt(Op.Val, 2, DAG).Val || // vspltish

7
lib/Target/PowerPC/PPCInstrAltivec.td
View File

@ -521,7 +521,7 @@ def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
"vxor $vD, $vD, $vD", VecFP,
[(set VRRC:$vD, (v4f32 immAllZerosV))]>;
[(set VRRC:$vD, (v4i32 immAllZerosV))]>;
}
//===----------------------------------------------------------------------===//
@ -544,9 +544,6 @@ def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>;
def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>;
def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;
def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0))>;
def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0))>;
def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0))>;
// Loads.
def : Pat<(v16i8 (load xoaddr:$src)), (v16i8 (LVX xoaddr:$src))>;
@ -637,7 +634,7 @@ def : Pat<(v8i16 (and VRRC:$A, (vnot VRRC:$B))),
(v8i16 (VANDC VRRC:$A, VRRC:$B))>;
def : Pat<(fmul VRRC:$vA, VRRC:$vB),
(VMADDFP VRRC:$vA, VRRC:$vB, (V_SET0))>;
(VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>;
// Fused multiply add and multiply sub for packed float. These are represented
// separately from the real instructions above, for operations that must have