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[mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5

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Differential Revision: http://reviews.llvm.org/D6419


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222887 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek 2014-11-27 14:41:44 +00:00
parent 72ba1af89c
commit 2b8e58cc82
4 changed files with 105 additions and 3 deletions
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60
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@ -287,6 +287,26 @@ static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeLiSimm7(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSimm4(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSimm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@ -1458,6 +1478,46 @@ static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
if (Value == 0)
Inst.addOperand(MCOperand::CreateImm(1));
else if (Value == 0x7)
Inst.addOperand(MCOperand::CreateImm(-1));
else
Inst.addOperand(MCOperand::CreateImm(Value << 2));
return MCDisassembler::Success;
}
static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(Value << 2));
return MCDisassembler::Success;
}
static DecodeStatus DecodeLiSimm7(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
if (Value == 0x7F)
Inst.addOperand(MCOperand::CreateImm(-1));
else
Inst.addOperand(MCOperand::CreateImm(Value));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm4(MCInst &Inst,
unsigned Value,
uint64_t Address,
const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
return MCDisassembler::Success;
}
static DecodeStatus DecodeSimm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,

12
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -1,7 +1,11 @@
def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
def simm4 : Operand<i32>;
def simm7 : Operand<i32>;
def simm4 : Operand<i32> {
let DecoderMethod = "DecodeSimm4";
}
def li_simm7 : Operand<i32> {
let DecoderMethod = "DecodeLiSimm7";
}
def simm12 : Operand<i32> {
let DecoderMethod = "DecodeSimm12";
@ -13,6 +17,7 @@ def uimm5_lsl2 : Operand<OtherVT> {
def uimm6_lsl2 : Operand<i32> {
let EncoderMethod = "getUImm6Lsl2Encoding";
let DecoderMethod = "DecodeUImm6Lsl2";
}
def simm9_addiusp : Operand<i32> {
@ -25,6 +30,7 @@ def uimm3_shift : Operand<i32> {
def simm3_lsa2 : Operand<i32> {
let EncoderMethod = "getSImm3Lsa2Value";
let DecoderMethod = "DecodeAddiur2Simm7";
}
def uimm4_andi : Operand<i32> {
@ -379,7 +385,7 @@ def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
def LI16_MM : LoadImmMM16<"li16", simm7, GPRMM16Opnd, immLi16>,
def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd, immLi16>,
LI_FM_MM16, IsAsCheapAsAMove;
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;

18
test/MC/Disassembler/Mips/micromips.txt
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@ -390,3 +390,21 @@
# CHECK: jr16 $9
0x45 0x89
# CHECK: li16 $3, -1
0xed 0xff
# CHECK: li16 $3, 126
0xed 0xfe
# CHECK: addiur1sp $7, 4
0x6f 0x83
# CHECK: addiur2 $6, $7, -1
0x6f 0x7e
# CHECK: addiur2 $6, $7, 12
0x6f 0x76
# CHECK: addius5 $7, -2
0x4c 0xfc

18
test/MC/Disassembler/Mips/micromips_le.txt
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@ -390,3 +390,21 @@
# CHECK: jr16 $9
0x89 0x45
# CHECK: li16 $3, -1
0xff 0xed
# CHECK: li16 $3, 126
0xfe 0xed
# CHECK: addiur1sp $7, 4
0x83 0x6f
# CHECK: addiur2 $6, $7, -1
0x7e 0x6f
# CHECK: addiur2 $6, $7, 12
0x76 0x6f
# CHECK: addius5 $7, -2
0xfc 0x4c