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Fix a major miscompilation where we were overwriting the scale reg.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19511 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-01-12 07:33:20 +00:00
parent 48034fd9f1
commit 2b9378646d
1 changed files with 1 additions and 1 deletions
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2
lib/Target/X86/X86ISelPattern.cpp
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@ -469,7 +469,7 @@ bool ISel::SelectAddress(SDOperand N, X86AddressMode &AM) {
AM.Disp += cast<ConstantSDNode>(N)->getValue();
return false;
case ISD::SHL:
if (AM.IndexReg == 0 || AM.Scale == 1)
if (AM.IndexReg == 0 && AM.Scale == 1)
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
unsigned Val = CN->getValue();
if (Val == 1 || Val == 2 || Val == 3) {