diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td
index ea6484985e6..b67218cf5ea 100644
--- a/lib/Target/ARM64/ARM64InstrFormats.td
+++ b/lib/Target/ARM64/ARM64InstrFormats.td
@@ -7451,7 +7451,7 @@ class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
 
 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
                        string asm, dag oops, dag iops>
-  : I<oops, iops, asm, "\t$Vt, $vaddr, $Xm", "", []> {
+  : I<oops, iops, asm, "\t$Vt, $vaddr, $Xm", "$vaddr = $wback", []> {
   bits<5> Vt;
   bits<5> vaddr;
   bits<5> Xm;
@@ -7465,7 +7465,6 @@ class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
   let Inst{11-10} = size;
   let Inst{9-5} = vaddr;
   let Inst{4-0} = Vt;
-  let DecoderMethod = "DecodeSIMDLdStPost";
 }
 
 // The immediate form of AdvSIMD post-indexed addressing is encoded with
@@ -7478,8 +7477,9 @@ multiclass SIMDLdStAliases<string asm, string layout, string Count,
   //      (LD1Twov8b_POST VecListTwo8b:$Vt, am_simdnoindex:$vaddr, XZR)
   def : InstAlias<asm # "\t$Vt, $vaddr, #" # Offset,
                   (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
+                      am_simdnoindex:$vaddr,
                       !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
-                      am_simdnoindex:$vaddr, XZR), 1>;
+                      XZR), 1>;
 
   // E.g. "ld1.8b { v0, v1 }, [x1], #16"
   //      "ld1.8b\t$Vt, $vaddr, #16"
@@ -7487,8 +7487,9 @@ multiclass SIMDLdStAliases<string asm, string layout, string Count,
   //      (LD1Twov8b_POST VecListTwo64:$Vt, am_simdnoindex:$vaddr, XZR)
   def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, #" # Offset,
                   (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
+                      am_simdnoindex:$vaddr,
                       !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
-                      am_simdnoindex:$vaddr, XZR), 0>;
+                      XZR), 0>;
 
   // E.g. "ld1.8b { v0, v1 }, [x1]"
   //      "ld1\t$Vt, $vaddr"
@@ -7505,8 +7506,8 @@ multiclass SIMDLdStAliases<string asm, string layout, string Count,
   //      (LD1Twov8b_POST VecListTwo64:$Vt, am_simdnoindex:$vaddr, GPR64pi8:$Xm)
   def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, $Xm",
                   (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
-                      !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
                       am_simdnoindex:$vaddr,
+                      !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
                       !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
 }
 
@@ -7537,31 +7538,38 @@ multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
 
 
     def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
-                       (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
+                       (outs am_simdnoindex:$wback,
+                             !cast<RegisterOperand>(veclist # "16b"):$Vt),
                        (ins am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
     def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
-                       (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
+                       (outs am_simdnoindex:$wback,
+                             !cast<RegisterOperand>(veclist # "8h"):$Vt),
                        (ins am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
     def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
-                       (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
+                       (outs am_simdnoindex:$wback,
+                             !cast<RegisterOperand>(veclist # "4s"):$Vt),
                        (ins am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
     def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
-                       (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
+                       (outs am_simdnoindex:$wback,
+                             !cast<RegisterOperand>(veclist # "2d"):$Vt),
                        (ins am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
     def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
-                       (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
+                       (outs am_simdnoindex:$wback,
+                             !cast<RegisterOperand>(veclist # "8b"):$Vt),
                        (ins am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
     def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
-                       (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
+                       (outs am_simdnoindex:$wback,
+                             !cast<RegisterOperand>(veclist # "4h"):$Vt),
                        (ins am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
     def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
-                       (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
+                       (outs am_simdnoindex:$wback,
+                             !cast<RegisterOperand>(veclist # "2s"):$Vt),
                        (ins am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
   }
@@ -7601,31 +7609,38 @@ multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
                            (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
                                 am_simdnoindex:$vaddr), []>;
 
-    def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm, (outs),
+    def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
+                       (outs am_simdnoindex:$wback),
                        (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
                             am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
-    def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm, (outs),
+    def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
+                       (outs am_simdnoindex:$wback),
                        (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
                             am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
-    def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm, (outs),
+    def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
+                       (outs am_simdnoindex:$wback),
                        (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
                             am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
-    def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm, (outs),
+    def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
+                       (outs am_simdnoindex:$wback),
                        (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
                             am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
-    def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm, (outs),
+    def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
+                       (outs am_simdnoindex:$wback),
                        (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
                             am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
-    def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm, (outs),
+    def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
+                       (outs am_simdnoindex:$wback),
                        (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
                             am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
-    def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm, (outs),
+    def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
+                       (outs am_simdnoindex:$wback),
                        (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
                             am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
@@ -7651,7 +7666,8 @@ multiclass BaseSIMDLd1<string Count, string asm, string veclist,
                            (ins am_simdnoindex:$vaddr), []>;
 
     def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
-                       (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
+                       (outs am_simdnoindex:$wback,
+                             !cast<RegisterOperand>(veclist # "1d"):$Vt),
                        (ins am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
   }
@@ -7669,7 +7685,8 @@ multiclass BaseSIMDSt1<string Count, string asm, string veclist,
                            (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
                                 am_simdnoindex:$vaddr), []>;
 
-    def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm, (outs),
+    def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
+                       (outs am_simdnoindex:$wback),
                        (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
                             am_simdnoindex:$vaddr,
                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
@@ -7721,9 +7738,9 @@ multiclass SIMDSt4Multiple<string asm> {
 //---
 
 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
-                         string asm, string operands, dag oops, dag iops,
-                         list<dag> pattern>
-  : I<oops, iops, asm, operands, "", pattern> {
+                         string asm, string operands, string cst,
+                         dag oops, dag iops, list<dag> pattern>
+  : I<oops, iops, asm, operands, cst, pattern> {
   bits<5> Vt;
   bits<5> vaddr;
   let Inst{31} = 0;
@@ -7733,13 +7750,12 @@ class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
   let Inst{15-13} = opcode;
   let Inst{9-5} = vaddr;
   let Inst{4-0} = Vt;
-  let DecoderMethod = "DecodeSIMDLdStSingle";
 }
 
 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
-                         string asm, string operands, dag oops, dag iops,
-                         list<dag> pattern>
-  : I<oops, iops, asm, operands, "$Vt = $dst", pattern> {
+                         string asm, string operands, string cst,
+                         dag oops, dag iops, list<dag> pattern>
+  : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
   bits<5> Vt;
   bits<5> vaddr;
   let Inst{31} = 0;
@@ -7749,15 +7765,15 @@ class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
   let Inst{15-13} = opcode;
   let Inst{9-5} = vaddr;
   let Inst{4-0} = Vt;
-  let DecoderMethod = "DecodeSIMDLdStSingleTied";
 }
 
 
 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
                   Operand listtype>
-  : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, $vaddr",
-                       (outs listtype:$Vt), (ins am_simdnoindex:$vaddr), []> {
+  : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, $vaddr", "",
+                       (outs listtype:$Vt), (ins am_simdnoindex:$vaddr),
+                       []> {
   let Inst{30} = Q;
   let Inst{23} = 0;
   let Inst{20-16} = 0b00000;
@@ -7768,7 +7784,8 @@ let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
                       string asm, Operand listtype, Operand GPR64pi>
   : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, $vaddr, $Xm",
-                       (outs listtype:$Vt),
+                       "$vaddr = $wback",
+                       (outs am_simdnoindex:$wback, listtype:$Vt),
                        (ins am_simdnoindex:$vaddr, GPR64pi:$Xm), []> {
   bits<5> Xm;
   let Inst{30} = Q;
@@ -7786,8 +7803,9 @@ multiclass SIMDLdrAliases<string asm, string layout, string Count,
   //      (LD1Rv8b_POST VecListOne8b:$Vt, am_simdnoindex:$vaddr, XZR)
   def : InstAlias<asm # "\t$Vt, $vaddr, #" # Offset,
                   (!cast<Instruction>(NAME # "v" # layout # "_POST")
+                      am_simdnoindex:$vaddr,
                       !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
-                      am_simdnoindex:$vaddr, XZR), 1>;
+                      XZR), 1>;
 
   // E.g. "ld1r.8b { v0 }, [x1], #1"
   //      "ld1r.8b\t$Vt, $vaddr, #1"
@@ -7795,8 +7813,9 @@ multiclass SIMDLdrAliases<string asm, string layout, string Count,
   //      (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, XZR)
   def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, #" # Offset,
                   (!cast<Instruction>(NAME # "v" # layout # "_POST")
+                      am_simdnoindex:$vaddr,
                       !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
-                      am_simdnoindex:$vaddr, XZR), 0>;
+                      XZR), 0>;
 
   // E.g. "ld1r.8b { v0 }, [x1]"
   //      "ld1r.8b\t$Vt, $vaddr"
@@ -7813,8 +7832,8 @@ multiclass SIMDLdrAliases<string asm, string layout, string Count,
   //      (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, GPR64pi1:$Xm)
   def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, $Xm",
                   (!cast<Instruction>(NAME # "v" # layout # "_POST")
-                      !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
                       am_simdnoindex:$vaddr,
+                      !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
                       !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
 }
 
@@ -7874,7 +7893,7 @@ multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
 
 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
                       dag oops, dag iops, list<dag> pattern>
-  : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
+  : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "", oops, iops,
                        pattern> {
   // idx encoded in Q:S:size fields.
   bits<4> idx;
@@ -7886,8 +7905,8 @@ class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
 }
 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
                       dag oops, dag iops, list<dag> pattern>
-  : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
-                       pattern> {
+  : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "",
+                           oops, iops, pattern> {
   // idx encoded in Q:S:size fields.
   bits<4> idx;
   let Inst{30} = idx{3};
@@ -7899,7 +7918,7 @@ class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
                           dag oops, dag iops>
   : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
-                       oops, iops, []> {
+                       "$vaddr = $wback", oops, iops, []> {
   // idx encoded in Q:S:size fields.
   bits<4> idx;
   bits<5> Xm;
@@ -7912,7 +7931,7 @@ class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
                           dag oops, dag iops>
   : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
-                       oops, iops, []> {
+                           "$vaddr = $wback", oops, iops, []> {
   // idx encoded in Q:S:size fields.
   bits<4> idx;
   bits<5> Xm;
@@ -7925,7 +7944,7 @@ class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
 
 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
                       dag oops, dag iops, list<dag> pattern>
-  : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
+  : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "", oops, iops,
                        pattern> {
   // idx encoded in Q:S:size<1> fields.
   bits<3> idx;
@@ -7938,8 +7957,8 @@ class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
 }
 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
                       dag oops, dag iops, list<dag> pattern>
-  : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
-                       pattern> {
+  : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "",
+                           oops, iops, pattern> {
   // idx encoded in Q:S:size<1> fields.
   bits<3> idx;
   let Inst{30} = idx{2};
@@ -7953,7 +7972,7 @@ class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
                           dag oops, dag iops>
   : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
-                       oops, iops, []> {
+                       "$vaddr = $wback", oops, iops, []> {
   // idx encoded in Q:S:size<1> fields.
   bits<3> idx;
   bits<5> Xm;
@@ -7967,7 +7986,7 @@ class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
                           dag oops, dag iops>
   : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
-                       oops, iops, []> {
+                           "$vaddr = $wback", oops, iops, []> {
   // idx encoded in Q:S:size<1> fields.
   bits<3> idx;
   bits<5> Xm;
@@ -7980,7 +7999,7 @@ class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm
 }
 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
                       dag oops, dag iops, list<dag> pattern>
-  : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
+  : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "", oops, iops,
                        pattern> {
   // idx encoded in Q:S fields.
   bits<2> idx;
@@ -7992,8 +8011,8 @@ class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
 }
 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
                       dag oops, dag iops, list<dag> pattern>
-  : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
-                       pattern> {
+  : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "",
+                           oops, iops, pattern> {
   // idx encoded in Q:S fields.
   bits<2> idx;
   let Inst{30} = idx{1};
@@ -8005,7 +8024,7 @@ class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm
 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
                           string asm, dag oops, dag iops>
   : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
-                       oops, iops, []> {
+                       "$vaddr = $wback", oops, iops, []> {
   // idx encoded in Q:S fields.
   bits<2> idx;
   bits<5> Xm;
@@ -8018,7 +8037,7 @@ class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
                           string asm, dag oops, dag iops>
   : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
-                       oops, iops, []> {
+                           "$vaddr = $wback", oops, iops, []> {
   // idx encoded in Q:S fields.
   bits<2> idx;
   bits<5> Xm;
@@ -8030,7 +8049,7 @@ class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
 }
 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
                       dag oops, dag iops, list<dag> pattern>
-  : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
+  : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "", oops, iops,
                        pattern> {
   // idx encoded in Q field.
   bits<1> idx;
@@ -8042,8 +8061,8 @@ class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
 }
 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
                       dag oops, dag iops, list<dag> pattern>
-  : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
-                       pattern> {
+  : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "",
+                           oops, iops, pattern> {
   // idx encoded in Q field.
   bits<1> idx;
   let Inst{30} = idx;
@@ -8055,7 +8074,7 @@ class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm
 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
                           string asm, dag oops, dag iops>
   : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
-                       oops, iops, []> {
+                       "$vaddr = $wback", oops, iops, []> {
   // idx encoded in Q field.
   bits<1> idx;
   bits<5> Xm;
@@ -8068,7 +8087,7 @@ class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
                           string asm, dag oops, dag iops>
   : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
-                       oops, iops, []> {
+                           "$vaddr = $wback", oops, iops, []> {
   // idx encoded in Q field.
   bits<1> idx;
   bits<5> Xm;
@@ -8089,7 +8108,7 @@ multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
                                 am_simdnoindex:$vaddr), []>;
 
   def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
-                            (outs listtype:$dst),
+                            (outs am_simdnoindex:$wback, listtype:$dst),
                             (ins listtype:$Vt, VectorIndexB:$idx,
                                  am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
 }
@@ -8103,7 +8122,7 @@ multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
                                  am_simdnoindex:$vaddr), []>;
 
   def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
-                            (outs listtype:$dst),
+                            (outs am_simdnoindex:$wback, listtype:$dst),
                             (ins listtype:$Vt, VectorIndexH:$idx,
                                  am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
 }
@@ -8117,7 +8136,7 @@ multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
                                  am_simdnoindex:$vaddr), []>;
 
   def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
-                            (outs listtype:$dst),
+                            (outs am_simdnoindex:$wback, listtype:$dst),
                             (ins listtype:$Vt, VectorIndexS:$idx,
                                  am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
 }
@@ -8130,7 +8149,7 @@ multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
                                  am_simdnoindex:$vaddr), []>;
 
   def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
-                            (outs listtype:$dst),
+                            (outs am_simdnoindex:$wback, listtype:$dst),
                             (ins listtype:$Vt, VectorIndexD:$idx,
                                  am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
 }
@@ -8142,7 +8161,8 @@ multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
                                         am_simdnoindex:$vaddr), []>;
 
   def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
-                            (outs), (ins listtype:$Vt, VectorIndexB:$idx,
+                                    (outs am_simdnoindex:$wback),
+                                    (ins listtype:$Vt, VectorIndexB:$idx,
                                          am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
 }
 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
@@ -8153,8 +8173,9 @@ multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
                                          am_simdnoindex:$vaddr), []>;
 
   def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
-                            (outs), (ins listtype:$Vt, VectorIndexH:$idx,
-                                         am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
+                            (outs am_simdnoindex:$wback),
+                            (ins listtype:$Vt, VectorIndexH:$idx,
+                                 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
 }
 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
@@ -8164,8 +8185,9 @@ multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
                                          am_simdnoindex:$vaddr), []>;
 
   def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
-                            (outs), (ins listtype:$Vt, VectorIndexS:$idx,
-                                         am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
+                            (outs am_simdnoindex:$wback),
+                            (ins listtype:$Vt, VectorIndexS:$idx,
+                                 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
 }
 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
@@ -8175,8 +8197,9 @@ multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
                                          am_simdnoindex:$vaddr), []>;
 
   def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
-                            (outs), (ins listtype:$Vt, VectorIndexD:$idx,
-                                         am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
+                            (outs am_simdnoindex:$wback),
+                            (ins listtype:$Vt, VectorIndexD:$idx,
+                                 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
 }
 
 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
@@ -8187,8 +8210,9 @@ multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
   //      (LD1Rv8b_POST VecListOne8b:$Vt, am_simdnoindex:$vaddr, XZR)
   def : InstAlias<asm # "\t$Vt$idx, $vaddr, #" # Offset,
                   (!cast<Instruction>(NAME # Type  # "_POST")
+                      am_simdnoindex:$vaddr,
                       !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
-                      idxtype:$idx, am_simdnoindex:$vaddr, XZR), 1>;
+                      idxtype:$idx, XZR), 1>;
 
   // E.g. "ld1.8b { v0 }[0], [x1], #1"
   //      "ld1.8b\t$Vt, $vaddr, #1"
@@ -8196,8 +8220,9 @@ multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
   //      (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, XZR)
   def : InstAlias<asm # "." # layout # "\t$Vt$idx, $vaddr, #" # Offset,
                   (!cast<Instruction>(NAME # Type # "_POST")
+                      am_simdnoindex:$vaddr,
                       !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
-                      idxtype:$idx, am_simdnoindex:$vaddr, XZR), 0>;
+                      idxtype:$idx, XZR), 0>;
 
   // E.g. "ld1.8b { v0 }[0], [x1]"
   //      "ld1.8b\t$Vt, $vaddr"
@@ -8214,8 +8239,9 @@ multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
   //      (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, GPR64pi1:$Xm)
   def : InstAlias<asm # "." # layout # "\t$Vt$idx, $vaddr, $Xm",
                       (!cast<Instruction>(NAME # Type # "_POST")
+                         am_simdnoindex:$vaddr,
                          !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
-                         idxtype:$idx, am_simdnoindex:$vaddr,
+                         idxtype:$idx,
                          !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
 }
 
diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index f53592a73aa..a7be9532fe8 100644
--- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -143,13 +143,6 @@ static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
                                                   const void *Decoder);
 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
                                         uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSIMDLdStPost(llvm::MCInst &Inst, uint32_t insn,
-                                       uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeSIMDLdStSingle(llvm::MCInst &Inst, uint32_t insn,
-                                         uint64_t Addr, const void *Decoder);
-static DecodeStatus DecodeSIMDLdStSingleTied(llvm::MCInst &Inst, uint32_t insn,
-                                             uint64_t Addr,
-                                             const void *Decoder);
 
 static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
                                          uint64_t Addr, const void *Decoder);
@@ -1455,567 +1448,3 @@ static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
 
   return Success;
 }
-
-static DecodeStatus DecodeSIMDLdStPost(llvm::MCInst &Inst, uint32_t insn,
-                                       uint64_t Addr, const void *Decoder) {
-  uint64_t Rd = fieldFromInstruction(insn, 0, 5);
-  uint64_t Rn = fieldFromInstruction(insn, 5, 5);
-  uint64_t Rm = fieldFromInstruction(insn, 16, 5);
-
-  switch (Inst.getOpcode()) {
-  default:
-    return Fail;
-  case ARM64::ST1Onev8b_POST:
-  case ARM64::ST1Onev4h_POST:
-  case ARM64::ST1Onev2s_POST:
-  case ARM64::ST1Onev1d_POST:
-  case ARM64::LD1Onev8b_POST:
-  case ARM64::LD1Onev4h_POST:
-  case ARM64::LD1Onev2s_POST:
-  case ARM64::LD1Onev1d_POST:
-    DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
-    break;
-  case ARM64::ST1Onev16b_POST:
-  case ARM64::ST1Onev8h_POST:
-  case ARM64::ST1Onev4s_POST:
-  case ARM64::ST1Onev2d_POST:
-  case ARM64::LD1Onev16b_POST:
-  case ARM64::LD1Onev8h_POST:
-  case ARM64::LD1Onev4s_POST:
-  case ARM64::LD1Onev2d_POST:
-    DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
-    break;
-  case ARM64::ST1Twov8b_POST:
-  case ARM64::ST1Twov4h_POST:
-  case ARM64::ST1Twov2s_POST:
-  case ARM64::ST1Twov1d_POST:
-  case ARM64::ST2Twov8b_POST:
-  case ARM64::ST2Twov4h_POST:
-  case ARM64::ST2Twov2s_POST:
-  case ARM64::LD1Twov8b_POST:
-  case ARM64::LD1Twov4h_POST:
-  case ARM64::LD1Twov2s_POST:
-  case ARM64::LD1Twov1d_POST:
-  case ARM64::LD2Twov8b_POST:
-  case ARM64::LD2Twov4h_POST:
-  case ARM64::LD2Twov2s_POST:
-    DecodeDDRegisterClass(Inst, Rd, Addr, Decoder);
-    break;
-  case ARM64::ST1Threev8b_POST:
-  case ARM64::ST1Threev4h_POST:
-  case ARM64::ST1Threev2s_POST:
-  case ARM64::ST1Threev1d_POST:
-  case ARM64::ST3Threev8b_POST:
-  case ARM64::ST3Threev4h_POST:
-  case ARM64::ST3Threev2s_POST:
-  case ARM64::LD1Threev8b_POST:
-  case ARM64::LD1Threev4h_POST:
-  case ARM64::LD1Threev2s_POST:
-  case ARM64::LD1Threev1d_POST:
-  case ARM64::LD3Threev8b_POST:
-  case ARM64::LD3Threev4h_POST:
-  case ARM64::LD3Threev2s_POST:
-    DecodeDDDRegisterClass(Inst, Rd, Addr, Decoder);
-    break;
-  case ARM64::ST1Fourv8b_POST:
-  case ARM64::ST1Fourv4h_POST:
-  case ARM64::ST1Fourv2s_POST:
-  case ARM64::ST1Fourv1d_POST:
-  case ARM64::ST4Fourv8b_POST:
-  case ARM64::ST4Fourv4h_POST:
-  case ARM64::ST4Fourv2s_POST:
-  case ARM64::LD1Fourv8b_POST:
-  case ARM64::LD1Fourv4h_POST:
-  case ARM64::LD1Fourv2s_POST:
-  case ARM64::LD1Fourv1d_POST:
-  case ARM64::LD4Fourv8b_POST:
-  case ARM64::LD4Fourv4h_POST:
-  case ARM64::LD4Fourv2s_POST:
-    DecodeDDDDRegisterClass(Inst, Rd, Addr, Decoder);
-    break;
-  case ARM64::ST1Twov16b_POST:
-  case ARM64::ST1Twov8h_POST:
-  case ARM64::ST1Twov4s_POST:
-  case ARM64::ST1Twov2d_POST:
-  case ARM64::ST2Twov16b_POST:
-  case ARM64::ST2Twov8h_POST:
-  case ARM64::ST2Twov4s_POST:
-  case ARM64::ST2Twov2d_POST:
-  case ARM64::LD1Twov16b_POST:
-  case ARM64::LD1Twov8h_POST:
-  case ARM64::LD1Twov4s_POST:
-  case ARM64::LD1Twov2d_POST:
-  case ARM64::LD2Twov16b_POST:
-  case ARM64::LD2Twov8h_POST:
-  case ARM64::LD2Twov4s_POST:
-  case ARM64::LD2Twov2d_POST:
-    DecodeQQRegisterClass(Inst, Rd, Addr, Decoder);
-    break;
-  case ARM64::ST1Threev16b_POST:
-  case ARM64::ST1Threev8h_POST:
-  case ARM64::ST1Threev4s_POST:
-  case ARM64::ST1Threev2d_POST:
-  case ARM64::ST3Threev16b_POST:
-  case ARM64::ST3Threev8h_POST:
-  case ARM64::ST3Threev4s_POST:
-  case ARM64::ST3Threev2d_POST:
-  case ARM64::LD1Threev16b_POST:
-  case ARM64::LD1Threev8h_POST:
-  case ARM64::LD1Threev4s_POST:
-  case ARM64::LD1Threev2d_POST:
-  case ARM64::LD3Threev16b_POST:
-  case ARM64::LD3Threev8h_POST:
-  case ARM64::LD3Threev4s_POST:
-  case ARM64::LD3Threev2d_POST:
-    DecodeQQQRegisterClass(Inst, Rd, Addr, Decoder);
-    break;
-  case ARM64::ST1Fourv16b_POST:
-  case ARM64::ST1Fourv8h_POST:
-  case ARM64::ST1Fourv4s_POST:
-  case ARM64::ST1Fourv2d_POST:
-  case ARM64::ST4Fourv16b_POST:
-  case ARM64::ST4Fourv8h_POST:
-  case ARM64::ST4Fourv4s_POST:
-  case ARM64::ST4Fourv2d_POST:
-  case ARM64::LD1Fourv16b_POST:
-  case ARM64::LD1Fourv8h_POST:
-  case ARM64::LD1Fourv4s_POST:
-  case ARM64::LD1Fourv2d_POST:
-  case ARM64::LD4Fourv16b_POST:
-  case ARM64::LD4Fourv8h_POST:
-  case ARM64::LD4Fourv4s_POST:
-  case ARM64::LD4Fourv2d_POST:
-    DecodeQQQQRegisterClass(Inst, Rd, Addr, Decoder);
-    break;
-  }
-
-  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
-  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
-  return Success;
-}
-
-static DecodeStatus DecodeSIMDLdStSingle(llvm::MCInst &Inst, uint32_t insn,
-                                         uint64_t Addr, const void *Decoder) {
-  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
-  uint64_t Rn = fieldFromInstruction(insn, 5, 5);
-  uint64_t Rm = fieldFromInstruction(insn, 16, 5);
-  uint64_t size = fieldFromInstruction(insn, 10, 2);
-  uint64_t S = fieldFromInstruction(insn, 12, 1);
-  uint64_t Q = fieldFromInstruction(insn, 30, 1);
-  uint64_t index = 0;
-
-  switch (Inst.getOpcode()) {
-  case ARM64::ST1i8:
-  case ARM64::ST1i8_POST:
-  case ARM64::ST2i8:
-  case ARM64::ST2i8_POST:
-  case ARM64::ST3i8_POST:
-  case ARM64::ST3i8:
-  case ARM64::ST4i8_POST:
-  case ARM64::ST4i8:
-    index = (Q << 3) | (S << 2) | size;
-    break;
-  case ARM64::ST1i16:
-  case ARM64::ST1i16_POST:
-  case ARM64::ST2i16:
-  case ARM64::ST2i16_POST:
-  case ARM64::ST3i16_POST:
-  case ARM64::ST3i16:
-  case ARM64::ST4i16_POST:
-  case ARM64::ST4i16:
-    index = (Q << 2) | (S << 1) | (size >> 1);
-    break;
-  case ARM64::ST1i32:
-  case ARM64::ST1i32_POST:
-  case ARM64::ST2i32:
-  case ARM64::ST2i32_POST:
-  case ARM64::ST3i32_POST:
-  case ARM64::ST3i32:
-  case ARM64::ST4i32_POST:
-  case ARM64::ST4i32:
-    index = (Q << 1) | S;
-    break;
-  case ARM64::ST1i64:
-  case ARM64::ST1i64_POST:
-  case ARM64::ST2i64:
-  case ARM64::ST2i64_POST:
-  case ARM64::ST3i64_POST:
-  case ARM64::ST3i64:
-  case ARM64::ST4i64_POST:
-  case ARM64::ST4i64:
-    index = Q;
-    break;
-  }
-
-  switch (Inst.getOpcode()) {
-  default:
-    return Fail;
-  case ARM64::LD1Rv8b:
-  case ARM64::LD1Rv8b_POST:
-  case ARM64::LD1Rv4h:
-  case ARM64::LD1Rv4h_POST:
-  case ARM64::LD1Rv2s:
-  case ARM64::LD1Rv2s_POST:
-  case ARM64::LD1Rv1d:
-  case ARM64::LD1Rv1d_POST:
-    DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD1Rv16b:
-  case ARM64::LD1Rv16b_POST:
-  case ARM64::LD1Rv8h:
-  case ARM64::LD1Rv8h_POST:
-  case ARM64::LD1Rv4s:
-  case ARM64::LD1Rv4s_POST:
-  case ARM64::LD1Rv2d:
-  case ARM64::LD1Rv2d_POST:
-  case ARM64::ST1i8:
-  case ARM64::ST1i8_POST:
-  case ARM64::ST1i16:
-  case ARM64::ST1i16_POST:
-  case ARM64::ST1i32:
-  case ARM64::ST1i32_POST:
-  case ARM64::ST1i64:
-  case ARM64::ST1i64_POST:
-    DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD2Rv16b:
-  case ARM64::LD2Rv16b_POST:
-  case ARM64::LD2Rv8h:
-  case ARM64::LD2Rv8h_POST:
-  case ARM64::LD2Rv4s:
-  case ARM64::LD2Rv4s_POST:
-  case ARM64::LD2Rv2d:
-  case ARM64::LD2Rv2d_POST:
-  case ARM64::ST2i8:
-  case ARM64::ST2i8_POST:
-  case ARM64::ST2i16:
-  case ARM64::ST2i16_POST:
-  case ARM64::ST2i32:
-  case ARM64::ST2i32_POST:
-  case ARM64::ST2i64:
-  case ARM64::ST2i64_POST:
-    DecodeQQRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD2Rv8b:
-  case ARM64::LD2Rv8b_POST:
-  case ARM64::LD2Rv4h:
-  case ARM64::LD2Rv4h_POST:
-  case ARM64::LD2Rv2s:
-  case ARM64::LD2Rv2s_POST:
-  case ARM64::LD2Rv1d:
-  case ARM64::LD2Rv1d_POST:
-    DecodeDDRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD3Rv8b:
-  case ARM64::LD3Rv8b_POST:
-  case ARM64::LD3Rv4h:
-  case ARM64::LD3Rv4h_POST:
-  case ARM64::LD3Rv2s:
-  case ARM64::LD3Rv2s_POST:
-  case ARM64::LD3Rv1d:
-  case ARM64::LD3Rv1d_POST:
-    DecodeDDDRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD3Rv16b:
-  case ARM64::LD3Rv16b_POST:
-  case ARM64::LD3Rv8h:
-  case ARM64::LD3Rv8h_POST:
-  case ARM64::LD3Rv4s:
-  case ARM64::LD3Rv4s_POST:
-  case ARM64::LD3Rv2d:
-  case ARM64::LD3Rv2d_POST:
-  case ARM64::ST3i8:
-  case ARM64::ST3i8_POST:
-  case ARM64::ST3i16:
-  case ARM64::ST3i16_POST:
-  case ARM64::ST3i32:
-  case ARM64::ST3i32_POST:
-  case ARM64::ST3i64:
-  case ARM64::ST3i64_POST:
-    DecodeQQQRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD4Rv8b:
-  case ARM64::LD4Rv8b_POST:
-  case ARM64::LD4Rv4h:
-  case ARM64::LD4Rv4h_POST:
-  case ARM64::LD4Rv2s:
-  case ARM64::LD4Rv2s_POST:
-  case ARM64::LD4Rv1d:
-  case ARM64::LD4Rv1d_POST:
-    DecodeDDDDRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD4Rv16b:
-  case ARM64::LD4Rv16b_POST:
-  case ARM64::LD4Rv8h:
-  case ARM64::LD4Rv8h_POST:
-  case ARM64::LD4Rv4s:
-  case ARM64::LD4Rv4s_POST:
-  case ARM64::LD4Rv2d:
-  case ARM64::LD4Rv2d_POST:
-  case ARM64::ST4i8:
-  case ARM64::ST4i8_POST:
-  case ARM64::ST4i16:
-  case ARM64::ST4i16_POST:
-  case ARM64::ST4i32:
-  case ARM64::ST4i32_POST:
-  case ARM64::ST4i64:
-  case ARM64::ST4i64_POST:
-    DecodeQQQQRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  }
-
-  switch (Inst.getOpcode()) {
-  case ARM64::LD1Rv8b:
-  case ARM64::LD1Rv8b_POST:
-  case ARM64::LD1Rv16b:
-  case ARM64::LD1Rv16b_POST:
-  case ARM64::LD1Rv4h:
-  case ARM64::LD1Rv4h_POST:
-  case ARM64::LD1Rv8h:
-  case ARM64::LD1Rv8h_POST:
-  case ARM64::LD1Rv4s:
-  case ARM64::LD1Rv4s_POST:
-  case ARM64::LD1Rv2s:
-  case ARM64::LD1Rv2s_POST:
-  case ARM64::LD1Rv1d:
-  case ARM64::LD1Rv1d_POST:
-  case ARM64::LD1Rv2d:
-  case ARM64::LD1Rv2d_POST:
-  case ARM64::LD2Rv8b:
-  case ARM64::LD2Rv8b_POST:
-  case ARM64::LD2Rv16b:
-  case ARM64::LD2Rv16b_POST:
-  case ARM64::LD2Rv4h:
-  case ARM64::LD2Rv4h_POST:
-  case ARM64::LD2Rv8h:
-  case ARM64::LD2Rv8h_POST:
-  case ARM64::LD2Rv2s:
-  case ARM64::LD2Rv2s_POST:
-  case ARM64::LD2Rv4s:
-  case ARM64::LD2Rv4s_POST:
-  case ARM64::LD2Rv2d:
-  case ARM64::LD2Rv2d_POST:
-  case ARM64::LD2Rv1d:
-  case ARM64::LD2Rv1d_POST:
-  case ARM64::LD3Rv8b:
-  case ARM64::LD3Rv8b_POST:
-  case ARM64::LD3Rv16b:
-  case ARM64::LD3Rv16b_POST:
-  case ARM64::LD3Rv4h:
-  case ARM64::LD3Rv4h_POST:
-  case ARM64::LD3Rv8h:
-  case ARM64::LD3Rv8h_POST:
-  case ARM64::LD3Rv2s:
-  case ARM64::LD3Rv2s_POST:
-  case ARM64::LD3Rv4s:
-  case ARM64::LD3Rv4s_POST:
-  case ARM64::LD3Rv2d:
-  case ARM64::LD3Rv2d_POST:
-  case ARM64::LD3Rv1d:
-  case ARM64::LD3Rv1d_POST:
-  case ARM64::LD4Rv8b:
-  case ARM64::LD4Rv8b_POST:
-  case ARM64::LD4Rv16b:
-  case ARM64::LD4Rv16b_POST:
-  case ARM64::LD4Rv4h:
-  case ARM64::LD4Rv4h_POST:
-  case ARM64::LD4Rv8h:
-  case ARM64::LD4Rv8h_POST:
-  case ARM64::LD4Rv2s:
-  case ARM64::LD4Rv2s_POST:
-  case ARM64::LD4Rv4s:
-  case ARM64::LD4Rv4s_POST:
-  case ARM64::LD4Rv2d:
-  case ARM64::LD4Rv2d_POST:
-  case ARM64::LD4Rv1d:
-  case ARM64::LD4Rv1d_POST:
-    break;
-  default:
-    Inst.addOperand(MCOperand::CreateImm(index));
-  }
-
-  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
-
-  switch (Inst.getOpcode()) {
-  case ARM64::ST1i8_POST:
-  case ARM64::ST1i16_POST:
-  case ARM64::ST1i32_POST:
-  case ARM64::ST1i64_POST:
-  case ARM64::LD1Rv8b_POST:
-  case ARM64::LD1Rv16b_POST:
-  case ARM64::LD1Rv4h_POST:
-  case ARM64::LD1Rv8h_POST:
-  case ARM64::LD1Rv2s_POST:
-  case ARM64::LD1Rv4s_POST:
-  case ARM64::LD1Rv1d_POST:
-  case ARM64::LD1Rv2d_POST:
-  case ARM64::ST2i8_POST:
-  case ARM64::ST2i16_POST:
-  case ARM64::ST2i32_POST:
-  case ARM64::ST2i64_POST:
-  case ARM64::LD2Rv8b_POST:
-  case ARM64::LD2Rv16b_POST:
-  case ARM64::LD2Rv4h_POST:
-  case ARM64::LD2Rv8h_POST:
-  case ARM64::LD2Rv2s_POST:
-  case ARM64::LD2Rv4s_POST:
-  case ARM64::LD2Rv2d_POST:
-  case ARM64::LD2Rv1d_POST:
-  case ARM64::ST3i8_POST:
-  case ARM64::ST3i16_POST:
-  case ARM64::ST3i32_POST:
-  case ARM64::ST3i64_POST:
-  case ARM64::LD3Rv8b_POST:
-  case ARM64::LD3Rv16b_POST:
-  case ARM64::LD3Rv4h_POST:
-  case ARM64::LD3Rv8h_POST:
-  case ARM64::LD3Rv2s_POST:
-  case ARM64::LD3Rv4s_POST:
-  case ARM64::LD3Rv2d_POST:
-  case ARM64::LD3Rv1d_POST:
-  case ARM64::ST4i8_POST:
-  case ARM64::ST4i16_POST:
-  case ARM64::ST4i32_POST:
-  case ARM64::ST4i64_POST:
-  case ARM64::LD4Rv8b_POST:
-  case ARM64::LD4Rv16b_POST:
-  case ARM64::LD4Rv4h_POST:
-  case ARM64::LD4Rv8h_POST:
-  case ARM64::LD4Rv2s_POST:
-  case ARM64::LD4Rv4s_POST:
-  case ARM64::LD4Rv2d_POST:
-  case ARM64::LD4Rv1d_POST:
-    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
-    break;
-  }
-  return Success;
-}
-
-static DecodeStatus DecodeSIMDLdStSingleTied(llvm::MCInst &Inst, uint32_t insn,
-                                             uint64_t Addr,
-                                             const void *Decoder) {
-  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
-  uint64_t Rn = fieldFromInstruction(insn, 5, 5);
-  uint64_t Rm = fieldFromInstruction(insn, 16, 5);
-  uint64_t size = fieldFromInstruction(insn, 10, 2);
-  uint64_t S = fieldFromInstruction(insn, 12, 1);
-  uint64_t Q = fieldFromInstruction(insn, 30, 1);
-  uint64_t index = 0;
-
-  switch (Inst.getOpcode()) {
-  case ARM64::LD1i8:
-  case ARM64::LD1i8_POST:
-  case ARM64::LD2i8:
-  case ARM64::LD2i8_POST:
-  case ARM64::LD3i8_POST:
-  case ARM64::LD3i8:
-  case ARM64::LD4i8_POST:
-  case ARM64::LD4i8:
-    index = (Q << 3) | (S << 2) | size;
-    break;
-  case ARM64::LD1i16:
-  case ARM64::LD1i16_POST:
-  case ARM64::LD2i16:
-  case ARM64::LD2i16_POST:
-  case ARM64::LD3i16_POST:
-  case ARM64::LD3i16:
-  case ARM64::LD4i16_POST:
-  case ARM64::LD4i16:
-    index = (Q << 2) | (S << 1) | (size >> 1);
-    break;
-  case ARM64::LD1i32:
-  case ARM64::LD1i32_POST:
-  case ARM64::LD2i32:
-  case ARM64::LD2i32_POST:
-  case ARM64::LD3i32_POST:
-  case ARM64::LD3i32:
-  case ARM64::LD4i32_POST:
-  case ARM64::LD4i32:
-    index = (Q << 1) | S;
-    break;
-  case ARM64::LD1i64:
-  case ARM64::LD1i64_POST:
-  case ARM64::LD2i64:
-  case ARM64::LD2i64_POST:
-  case ARM64::LD3i64_POST:
-  case ARM64::LD3i64:
-  case ARM64::LD4i64_POST:
-  case ARM64::LD4i64:
-    index = Q;
-    break;
-  }
-
-  switch (Inst.getOpcode()) {
-  default:
-    return Fail;
-  case ARM64::LD1i8:
-  case ARM64::LD1i8_POST:
-  case ARM64::LD1i16:
-  case ARM64::LD1i16_POST:
-  case ARM64::LD1i32:
-  case ARM64::LD1i32_POST:
-  case ARM64::LD1i64:
-  case ARM64::LD1i64_POST:
-    DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
-    DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD2i8:
-  case ARM64::LD2i8_POST:
-  case ARM64::LD2i16:
-  case ARM64::LD2i16_POST:
-  case ARM64::LD2i32:
-  case ARM64::LD2i32_POST:
-  case ARM64::LD2i64:
-  case ARM64::LD2i64_POST:
-    DecodeQQRegisterClass(Inst, Rt, Addr, Decoder);
-    DecodeQQRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD3i8:
-  case ARM64::LD3i8_POST:
-  case ARM64::LD3i16:
-  case ARM64::LD3i16_POST:
-  case ARM64::LD3i32:
-  case ARM64::LD3i32_POST:
-  case ARM64::LD3i64:
-  case ARM64::LD3i64_POST:
-    DecodeQQQRegisterClass(Inst, Rt, Addr, Decoder);
-    DecodeQQQRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  case ARM64::LD4i8:
-  case ARM64::LD4i8_POST:
-  case ARM64::LD4i16:
-  case ARM64::LD4i16_POST:
-  case ARM64::LD4i32:
-  case ARM64::LD4i32_POST:
-  case ARM64::LD4i64:
-  case ARM64::LD4i64_POST:
-    DecodeQQQQRegisterClass(Inst, Rt, Addr, Decoder);
-    DecodeQQQQRegisterClass(Inst, Rt, Addr, Decoder);
-    break;
-  }
-
-  Inst.addOperand(MCOperand::CreateImm(index));
-  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
-
-  switch (Inst.getOpcode()) {
-  case ARM64::LD1i8_POST:
-  case ARM64::LD1i16_POST:
-  case ARM64::LD1i32_POST:
-  case ARM64::LD1i64_POST:
-  case ARM64::LD2i8_POST:
-  case ARM64::LD2i16_POST:
-  case ARM64::LD2i32_POST:
-  case ARM64::LD2i64_POST:
-  case ARM64::LD3i8_POST:
-  case ARM64::LD3i16_POST:
-  case ARM64::LD3i32_POST:
-  case ARM64::LD3i64_POST:
-  case ARM64::LD4i8_POST:
-  case ARM64::LD4i16_POST:
-  case ARM64::LD4i32_POST:
-  case ARM64::LD4i64_POST:
-    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
-    break;
-  }
-  return Success;
-}
diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
index a9ba7d277d4..cee3adc4eed 100644
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
@@ -390,351 +390,352 @@ struct LdStNInstrDesc {
   unsigned Opcode;
   const char *Mnemonic;
   const char *Layout;
-  int LaneOperand;
+  int ListOperand;
+  bool HasLane;
   int NaturalOffset;
 };
 
 static LdStNInstrDesc LdStNInstInfo[] = {
-  { ARM64::LD1i8,             "ld1",  ".b",     2, 0  },
-  { ARM64::LD1i16,            "ld1",  ".h",     2, 0  },
-  { ARM64::LD1i32,            "ld1",  ".s",     2, 0  },
-  { ARM64::LD1i64,            "ld1",  ".d",     2, 0  },
-  { ARM64::LD1i8_POST,        "ld1",  ".b",     2, 1  },
-  { ARM64::LD1i16_POST,       "ld1",  ".h",     2, 2  },
-  { ARM64::LD1i32_POST,       "ld1",  ".s",     2, 4  },
-  { ARM64::LD1i64_POST,       "ld1",  ".d",     2, 8  },
-  { ARM64::LD1Rv16b,          "ld1r", ".16b",   0, 0  },
-  { ARM64::LD1Rv8h,           "ld1r", ".8h",    0, 0  },
-  { ARM64::LD1Rv4s,           "ld1r", ".4s",    0, 0  },
-  { ARM64::LD1Rv2d,           "ld1r", ".2d",    0, 0  },
-  { ARM64::LD1Rv8b,           "ld1r", ".8b",    0, 0  },
-  { ARM64::LD1Rv4h,           "ld1r", ".4h",    0, 0  },
-  { ARM64::LD1Rv2s,           "ld1r", ".2s",    0, 0  },
-  { ARM64::LD1Rv1d,           "ld1r", ".1d",    0, 0  },
-  { ARM64::LD1Rv16b_POST,     "ld1r", ".16b",   0, 1  },
-  { ARM64::LD1Rv8h_POST,      "ld1r", ".8h",    0, 2  },
-  { ARM64::LD1Rv4s_POST,      "ld1r", ".4s",    0, 4  },
-  { ARM64::LD1Rv2d_POST,      "ld1r", ".2d",    0, 8  },
-  { ARM64::LD1Rv8b_POST,      "ld1r", ".8b",    0, 1  },
-  { ARM64::LD1Rv4h_POST,      "ld1r", ".4h",    0, 2  },
-  { ARM64::LD1Rv2s_POST,      "ld1r", ".2s",    0, 4  },
-  { ARM64::LD1Rv1d_POST,      "ld1r", ".1d",    0, 8  },
-  { ARM64::LD1Onev16b,        "ld1",  ".16b",   0, 0  },
-  { ARM64::LD1Onev8h,         "ld1",  ".8h",    0, 0  },
-  { ARM64::LD1Onev4s,         "ld1",  ".4s",    0, 0  },
-  { ARM64::LD1Onev2d,         "ld1",  ".2d",    0, 0  },
-  { ARM64::LD1Onev8b,         "ld1",  ".8b",    0, 0  },
-  { ARM64::LD1Onev4h,         "ld1",  ".4h",    0, 0  },
-  { ARM64::LD1Onev2s,         "ld1",  ".2s",    0, 0  },
-  { ARM64::LD1Onev1d,         "ld1",  ".1d",    0, 0  },
-  { ARM64::LD1Onev16b_POST,   "ld1",  ".16b",   0, 16 },
-  { ARM64::LD1Onev8h_POST,    "ld1",  ".8h",    0, 16 },
-  { ARM64::LD1Onev4s_POST,    "ld1",  ".4s",    0, 16 },
-  { ARM64::LD1Onev2d_POST,    "ld1",  ".2d",    0, 16 },
-  { ARM64::LD1Onev8b_POST,    "ld1",  ".8b",    0, 8  },
-  { ARM64::LD1Onev4h_POST,    "ld1",  ".4h",    0, 8  },
-  { ARM64::LD1Onev2s_POST,    "ld1",  ".2s",    0, 8  },
-  { ARM64::LD1Onev1d_POST,    "ld1",  ".1d",    0, 8  },
-  { ARM64::LD1Twov16b,        "ld1",  ".16b",   0, 0  },
-  { ARM64::LD1Twov8h,         "ld1",  ".8h",    0, 0  },
-  { ARM64::LD1Twov4s,         "ld1",  ".4s",    0, 0  },
-  { ARM64::LD1Twov2d,         "ld1",  ".2d",    0, 0  },
-  { ARM64::LD1Twov8b,         "ld1",  ".8b",    0, 0  },
-  { ARM64::LD1Twov4h,         "ld1",  ".4h",    0, 0  },
-  { ARM64::LD1Twov2s,         "ld1",  ".2s",    0, 0  },
-  { ARM64::LD1Twov1d,         "ld1",  ".1d",    0, 0  },
-  { ARM64::LD1Twov16b_POST,   "ld1",  ".16b",   0, 32 },
-  { ARM64::LD1Twov8h_POST,    "ld1",  ".8h",    0, 32 },
-  { ARM64::LD1Twov4s_POST,    "ld1",  ".4s",    0, 32 },
-  { ARM64::LD1Twov2d_POST,    "ld1",  ".2d",    0, 32 },
-  { ARM64::LD1Twov8b_POST,    "ld1",  ".8b",    0, 16 },
-  { ARM64::LD1Twov4h_POST,    "ld1",  ".4h",    0, 16 },
-  { ARM64::LD1Twov2s_POST,    "ld1",  ".2s",    0, 16 },
-  { ARM64::LD1Twov1d_POST,    "ld1",  ".1d",    0, 16 },
-  { ARM64::LD1Threev16b,      "ld1",  ".16b",   0, 0  },
-  { ARM64::LD1Threev8h,       "ld1",  ".8h",    0, 0  },
-  { ARM64::LD1Threev4s,       "ld1",  ".4s",    0, 0  },
-  { ARM64::LD1Threev2d,       "ld1",  ".2d",    0, 0  },
-  { ARM64::LD1Threev8b,       "ld1",  ".8b",    0, 0  },
-  { ARM64::LD1Threev4h,       "ld1",  ".4h",    0, 0  },
-  { ARM64::LD1Threev2s,       "ld1",  ".2s",    0, 0  },
-  { ARM64::LD1Threev1d,       "ld1",  ".1d",    0, 0  },
-  { ARM64::LD1Threev16b_POST, "ld1",  ".16b",   0, 48 },
-  { ARM64::LD1Threev8h_POST,  "ld1",  ".8h",    0, 48 },
-  { ARM64::LD1Threev4s_POST,  "ld1",  ".4s",    0, 48 },
-  { ARM64::LD1Threev2d_POST,  "ld1",  ".2d",    0, 48 },
-  { ARM64::LD1Threev8b_POST,  "ld1",  ".8b",    0, 24 },
-  { ARM64::LD1Threev4h_POST,  "ld1",  ".4h",    0, 24 },
-  { ARM64::LD1Threev2s_POST,  "ld1",  ".2s",    0, 24 },
-  { ARM64::LD1Threev1d_POST,  "ld1",  ".1d",    0, 24 },
-  { ARM64::LD1Fourv16b,       "ld1",  ".16b",   0, 0  },
-  { ARM64::LD1Fourv8h,        "ld1",  ".8h",    0, 0  },
-  { ARM64::LD1Fourv4s,        "ld1",  ".4s",    0, 0  },
-  { ARM64::LD1Fourv2d,        "ld1",  ".2d",    0, 0  },
-  { ARM64::LD1Fourv8b,        "ld1",  ".8b",    0, 0  },
-  { ARM64::LD1Fourv4h,        "ld1",  ".4h",    0, 0  },
-  { ARM64::LD1Fourv2s,        "ld1",  ".2s",    0, 0  },
-  { ARM64::LD1Fourv1d,        "ld1",  ".1d",    0, 0  },
-  { ARM64::LD1Fourv16b_POST,  "ld1",  ".16b",   0, 64 },
-  { ARM64::LD1Fourv8h_POST,   "ld1",  ".8h",    0, 64 },
-  { ARM64::LD1Fourv4s_POST,   "ld1",  ".4s",    0, 64 },
-  { ARM64::LD1Fourv2d_POST,   "ld1",  ".2d",    0, 64 },
-  { ARM64::LD1Fourv8b_POST,   "ld1",  ".8b",    0, 32 },
-  { ARM64::LD1Fourv4h_POST,   "ld1",  ".4h",    0, 32 },
-  { ARM64::LD1Fourv2s_POST,   "ld1",  ".2s",    0, 32 },
-  { ARM64::LD1Fourv1d_POST,   "ld1",  ".1d",    0, 32 },
-  { ARM64::LD2i8,             "ld2",  ".b",     2, 0  },
-  { ARM64::LD2i16,            "ld2",  ".h",     2, 0  },
-  { ARM64::LD2i32,            "ld2",  ".s",     2, 0  },
-  { ARM64::LD2i64,            "ld2",  ".d",     2, 0  },
-  { ARM64::LD2i8_POST,        "ld2",  ".b",     2, 2  },
-  { ARM64::LD2i16_POST,       "ld2",  ".h",     2, 4  },
-  { ARM64::LD2i32_POST,       "ld2",  ".s",     2, 8  },
-  { ARM64::LD2i64_POST,       "ld2",  ".d",     2, 16  },
-  { ARM64::LD2Rv16b,          "ld2r", ".16b",   0, 0  },
-  { ARM64::LD2Rv8h,           "ld2r", ".8h",    0, 0  },
-  { ARM64::LD2Rv4s,           "ld2r", ".4s",    0, 0  },
-  { ARM64::LD2Rv2d,           "ld2r", ".2d",    0, 0  },
-  { ARM64::LD2Rv8b,           "ld2r", ".8b",    0, 0  },
-  { ARM64::LD2Rv4h,           "ld2r", ".4h",    0, 0  },
-  { ARM64::LD2Rv2s,           "ld2r", ".2s",    0, 0  },
-  { ARM64::LD2Rv1d,           "ld2r", ".1d",    0, 0  },
-  { ARM64::LD2Rv16b_POST,     "ld2r", ".16b",   0, 2  },
-  { ARM64::LD2Rv8h_POST,      "ld2r", ".8h",    0, 4  },
-  { ARM64::LD2Rv4s_POST,      "ld2r", ".4s",    0, 8  },
-  { ARM64::LD2Rv2d_POST,      "ld2r", ".2d",    0, 16 },
-  { ARM64::LD2Rv8b_POST,      "ld2r", ".8b",    0, 2  },
-  { ARM64::LD2Rv4h_POST,      "ld2r", ".4h",    0, 4  },
-  { ARM64::LD2Rv2s_POST,      "ld2r", ".2s",    0, 8  },
-  { ARM64::LD2Rv1d_POST,      "ld2r", ".1d",    0, 16 },
-  { ARM64::LD2Twov16b,        "ld2",  ".16b",   0, 0  },
-  { ARM64::LD2Twov8h,         "ld2",  ".8h",    0, 0  },
-  { ARM64::LD2Twov4s,         "ld2",  ".4s",    0, 0  },
-  { ARM64::LD2Twov2d,         "ld2",  ".2d",    0, 0  },
-  { ARM64::LD2Twov8b,         "ld2",  ".8b",    0, 0  },
-  { ARM64::LD2Twov4h,         "ld2",  ".4h",    0, 0  },
-  { ARM64::LD2Twov2s,         "ld2",  ".2s",    0, 0  },
-  { ARM64::LD2Twov16b_POST,   "ld2",  ".16b",   0, 32 },
-  { ARM64::LD2Twov8h_POST,    "ld2",  ".8h",    0, 32 },
-  { ARM64::LD2Twov4s_POST,    "ld2",  ".4s",    0, 32 },
-  { ARM64::LD2Twov2d_POST,    "ld2",  ".2d",    0, 32 },
-  { ARM64::LD2Twov8b_POST,    "ld2",  ".8b",    0, 16 },
-  { ARM64::LD2Twov4h_POST,    "ld2",  ".4h",    0, 16 },
-  { ARM64::LD2Twov2s_POST,    "ld2",  ".2s",    0, 16 },
-  { ARM64::LD3i8,             "ld3",  ".b",     2, 0  },
-  { ARM64::LD3i16,            "ld3",  ".h",     2, 0  },
-  { ARM64::LD3i32,            "ld3",  ".s",     2, 0  },
-  { ARM64::LD3i64,            "ld3",  ".d",     2, 0  },
-  { ARM64::LD3i8_POST,        "ld3",  ".b",     2, 3  },
-  { ARM64::LD3i16_POST,       "ld3",  ".h",     2, 6  },
-  { ARM64::LD3i32_POST,       "ld3",  ".s",     2, 12  },
-  { ARM64::LD3i64_POST,       "ld3",  ".d",     2, 24  },
-  { ARM64::LD3Rv16b,          "ld3r", ".16b",   0, 0  },
-  { ARM64::LD3Rv8h,           "ld3r", ".8h",    0, 0  },
-  { ARM64::LD3Rv4s,           "ld3r", ".4s",    0, 0  },
-  { ARM64::LD3Rv2d,           "ld3r", ".2d",    0, 0  },
-  { ARM64::LD3Rv8b,           "ld3r", ".8b",    0, 0  },
-  { ARM64::LD3Rv4h,           "ld3r", ".4h",    0, 0  },
-  { ARM64::LD3Rv2s,           "ld3r", ".2s",    0, 0  },
-  { ARM64::LD3Rv1d,           "ld3r", ".1d",    0, 0  },
-  { ARM64::LD3Rv16b_POST,     "ld3r", ".16b",   0, 3  },
-  { ARM64::LD3Rv8h_POST,      "ld3r", ".8h",    0, 6  },
-  { ARM64::LD3Rv4s_POST,      "ld3r", ".4s",    0, 12 },
-  { ARM64::LD3Rv2d_POST,      "ld3r", ".2d",    0, 24 },
-  { ARM64::LD3Rv8b_POST,      "ld3r", ".8b",    0, 3  },
-  { ARM64::LD3Rv4h_POST,      "ld3r", ".4h",    0, 6  },
-  { ARM64::LD3Rv2s_POST,      "ld3r", ".2s",    0, 12 },
-  { ARM64::LD3Rv1d_POST,      "ld3r", ".1d",    0, 24 },
-  { ARM64::LD3Threev16b,      "ld3",  ".16b",   0, 0  },
-  { ARM64::LD3Threev8h,       "ld3",  ".8h",    0, 0  },
-  { ARM64::LD3Threev4s,       "ld3",  ".4s",    0, 0  },
-  { ARM64::LD3Threev2d,       "ld3",  ".2d",    0, 0  },
-  { ARM64::LD3Threev8b,       "ld3",  ".8b",    0, 0  },
-  { ARM64::LD3Threev4h,       "ld3",  ".4h",    0, 0  },
-  { ARM64::LD3Threev2s,       "ld3",  ".2s",    0, 0  },
-  { ARM64::LD3Threev16b_POST, "ld3",  ".16b",   0, 48 },
-  { ARM64::LD3Threev8h_POST,  "ld3",  ".8h",    0, 48 },
-  { ARM64::LD3Threev4s_POST,  "ld3",  ".4s",    0, 48 },
-  { ARM64::LD3Threev2d_POST,  "ld3",  ".2d",    0, 48 },
-  { ARM64::LD3Threev8b_POST,  "ld3",  ".8b",    0, 24 },
-  { ARM64::LD3Threev4h_POST,  "ld3",  ".4h",    0, 24 },
-  { ARM64::LD3Threev2s_POST,  "ld3",  ".2s",    0, 24 },
-  { ARM64::LD4i8,             "ld4",  ".b",     2, 0  },
-  { ARM64::LD4i16,            "ld4",  ".h",     2, 0  },
-  { ARM64::LD4i32,            "ld4",  ".s",     2, 0  },
-  { ARM64::LD4i64,            "ld4",  ".d",     2, 0  },
-  { ARM64::LD4i8_POST,        "ld4",  ".b",     2, 4  },
-  { ARM64::LD4i16_POST,       "ld4",  ".h",     2, 8  },
-  { ARM64::LD4i32_POST,       "ld4",  ".s",     2, 16 },
-  { ARM64::LD4i64_POST,       "ld4",  ".d",     2, 32 },
-  { ARM64::LD4Rv16b,          "ld4r", ".16b",   0, 0  },
-  { ARM64::LD4Rv8h,           "ld4r", ".8h",    0, 0  },
-  { ARM64::LD4Rv4s,           "ld4r", ".4s",    0, 0  },
-  { ARM64::LD4Rv2d,           "ld4r", ".2d",    0, 0  },
-  { ARM64::LD4Rv8b,           "ld4r", ".8b",    0, 0  },
-  { ARM64::LD4Rv4h,           "ld4r", ".4h",    0, 0  },
-  { ARM64::LD4Rv2s,           "ld4r", ".2s",    0, 0  },
-  { ARM64::LD4Rv1d,           "ld4r", ".1d",    0, 0  },
-  { ARM64::LD4Rv16b_POST,     "ld4r", ".16b",   0, 4  },
-  { ARM64::LD4Rv8h_POST,      "ld4r", ".8h",    0, 8  },
-  { ARM64::LD4Rv4s_POST,      "ld4r", ".4s",    0, 16 },
-  { ARM64::LD4Rv2d_POST,      "ld4r", ".2d",    0, 32 },
-  { ARM64::LD4Rv8b_POST,      "ld4r", ".8b",    0, 4  },
-  { ARM64::LD4Rv4h_POST,      "ld4r", ".4h",    0, 8  },
-  { ARM64::LD4Rv2s_POST,      "ld4r", ".2s",    0, 16 },
-  { ARM64::LD4Rv1d_POST,      "ld4r", ".1d",    0, 32 },
-  { ARM64::LD4Fourv16b,       "ld4",  ".16b",   0, 0  },
-  { ARM64::LD4Fourv8h,        "ld4",  ".8h",    0, 0  },
-  { ARM64::LD4Fourv4s,        "ld4",  ".4s",    0, 0  },
-  { ARM64::LD4Fourv2d,        "ld4",  ".2d",    0, 0  },
-  { ARM64::LD4Fourv8b,        "ld4",  ".8b",    0, 0  },
-  { ARM64::LD4Fourv4h,        "ld4",  ".4h",    0, 0  },
-  { ARM64::LD4Fourv2s,        "ld4",  ".2s",    0, 0  },
-  { ARM64::LD4Fourv16b_POST,  "ld4",  ".16b",   0, 64 },
-  { ARM64::LD4Fourv8h_POST,   "ld4",  ".8h",    0, 64 },
-  { ARM64::LD4Fourv4s_POST,   "ld4",  ".4s",    0, 64 },
-  { ARM64::LD4Fourv2d_POST,   "ld4",  ".2d",    0, 64 },
-  { ARM64::LD4Fourv8b_POST,   "ld4",  ".8b",    0, 32 },
-  { ARM64::LD4Fourv4h_POST,   "ld4",  ".4h",    0, 32 },
-  { ARM64::LD4Fourv2s_POST,   "ld4",  ".2s",    0, 32 },
-  { ARM64::ST1i8,             "st1",  ".b",     1, 0  },
-  { ARM64::ST1i16,            "st1",  ".h",     1, 0  },
-  { ARM64::ST1i32,            "st1",  ".s",     1, 0  },
-  { ARM64::ST1i64,            "st1",  ".d",     1, 0  },
-  { ARM64::ST1i8_POST,        "st1",  ".b",     1, 1  },
-  { ARM64::ST1i16_POST,       "st1",  ".h",     1, 2  },
-  { ARM64::ST1i32_POST,       "st1",  ".s",     1, 4  },
-  { ARM64::ST1i64_POST,       "st1",  ".d",     1, 8  },
-  { ARM64::ST1Onev16b,        "st1",  ".16b",   0, 0  },
-  { ARM64::ST1Onev8h,         "st1",  ".8h",    0, 0  },
-  { ARM64::ST1Onev4s,         "st1",  ".4s",    0, 0  },
-  { ARM64::ST1Onev2d,         "st1",  ".2d",    0, 0  },
-  { ARM64::ST1Onev8b,         "st1",  ".8b",    0, 0  },
-  { ARM64::ST1Onev4h,         "st1",  ".4h",    0, 0  },
-  { ARM64::ST1Onev2s,         "st1",  ".2s",    0, 0  },
-  { ARM64::ST1Onev1d,         "st1",  ".1d",    0, 0  },
-  { ARM64::ST1Onev16b_POST,   "st1",  ".16b",   0, 16 },
-  { ARM64::ST1Onev8h_POST,    "st1",  ".8h",    0, 16 },
-  { ARM64::ST1Onev4s_POST,    "st1",  ".4s",    0, 16 },
-  { ARM64::ST1Onev2d_POST,    "st1",  ".2d",    0, 16 },
-  { ARM64::ST1Onev8b_POST,    "st1",  ".8b",    0, 8  },
-  { ARM64::ST1Onev4h_POST,    "st1",  ".4h",    0, 8  },
-  { ARM64::ST1Onev2s_POST,    "st1",  ".2s",    0, 8  },
-  { ARM64::ST1Onev1d_POST,    "st1",  ".1d",    0, 8  },
-  { ARM64::ST1Twov16b,        "st1",  ".16b",   0, 0  },
-  { ARM64::ST1Twov8h,         "st1",  ".8h",    0, 0  },
-  { ARM64::ST1Twov4s,         "st1",  ".4s",    0, 0  },
-  { ARM64::ST1Twov2d,         "st1",  ".2d",    0, 0  },
-  { ARM64::ST1Twov8b,         "st1",  ".8b",    0, 0  },
-  { ARM64::ST1Twov4h,         "st1",  ".4h",    0, 0  },
-  { ARM64::ST1Twov2s,         "st1",  ".2s",    0, 0  },
-  { ARM64::ST1Twov1d,         "st1",  ".1d",    0, 0  },
-  { ARM64::ST1Twov16b_POST,   "st1",  ".16b",   0, 32 },
-  { ARM64::ST1Twov8h_POST,    "st1",  ".8h",    0, 32 },
-  { ARM64::ST1Twov4s_POST,    "st1",  ".4s",    0, 32 },
-  { ARM64::ST1Twov2d_POST,    "st1",  ".2d",    0, 32 },
-  { ARM64::ST1Twov8b_POST,    "st1",  ".8b",    0, 16 },
-  { ARM64::ST1Twov4h_POST,    "st1",  ".4h",    0, 16 },
-  { ARM64::ST1Twov2s_POST,    "st1",  ".2s",    0, 16 },
-  { ARM64::ST1Twov1d_POST,    "st1",  ".1d",    0, 16 },
-  { ARM64::ST1Threev16b,      "st1",  ".16b",   0, 0  },
-  { ARM64::ST1Threev8h,       "st1",  ".8h",    0, 0  },
-  { ARM64::ST1Threev4s,       "st1",  ".4s",    0, 0  },
-  { ARM64::ST1Threev2d,       "st1",  ".2d",    0, 0  },
-  { ARM64::ST1Threev8b,       "st1",  ".8b",    0, 0  },
-  { ARM64::ST1Threev4h,       "st1",  ".4h",    0, 0  },
-  { ARM64::ST1Threev2s,       "st1",  ".2s",    0, 0  },
-  { ARM64::ST1Threev1d,       "st1",  ".1d",    0, 0  },
-  { ARM64::ST1Threev16b_POST, "st1",  ".16b",   0, 48 },
-  { ARM64::ST1Threev8h_POST,  "st1",  ".8h",    0, 48 },
-  { ARM64::ST1Threev4s_POST,  "st1",  ".4s",    0, 48 },
-  { ARM64::ST1Threev2d_POST,  "st1",  ".2d",    0, 48 },
-  { ARM64::ST1Threev8b_POST,  "st1",  ".8b",    0, 24 },
-  { ARM64::ST1Threev4h_POST,  "st1",  ".4h",    0, 24 },
-  { ARM64::ST1Threev2s_POST,  "st1",  ".2s",    0, 24 },
-  { ARM64::ST1Threev1d_POST,  "st1",  ".1d",    0, 24 },
-  { ARM64::ST1Fourv16b,       "st1",  ".16b",   0, 0  },
-  { ARM64::ST1Fourv8h,        "st1",  ".8h",    0, 0  },
-  { ARM64::ST1Fourv4s,        "st1",  ".4s",    0, 0  },
-  { ARM64::ST1Fourv2d,        "st1",  ".2d",    0, 0  },
-  { ARM64::ST1Fourv8b,        "st1",  ".8b",    0, 0  },
-  { ARM64::ST1Fourv4h,        "st1",  ".4h",    0, 0  },
-  { ARM64::ST1Fourv2s,        "st1",  ".2s",    0, 0  },
-  { ARM64::ST1Fourv1d,        "st1",  ".1d",    0, 0  },
-  { ARM64::ST1Fourv16b_POST,  "st1",  ".16b",   0, 64 },
-  { ARM64::ST1Fourv8h_POST,   "st1",  ".8h",    0, 64 },
-  { ARM64::ST1Fourv4s_POST,   "st1",  ".4s",    0, 64 },
-  { ARM64::ST1Fourv2d_POST,   "st1",  ".2d",    0, 64 },
-  { ARM64::ST1Fourv8b_POST,   "st1",  ".8b",    0, 32 },
-  { ARM64::ST1Fourv4h_POST,   "st1",  ".4h",    0, 32 },
-  { ARM64::ST1Fourv2s_POST,   "st1",  ".2s",    0, 32 },
-  { ARM64::ST1Fourv1d_POST,   "st1",  ".1d",    0, 32 },
-  { ARM64::ST2i8,             "st2",  ".b",     1, 0  },
-  { ARM64::ST2i16,            "st2",  ".h",     1, 0  },
-  { ARM64::ST2i32,            "st2",  ".s",     1, 0  },
-  { ARM64::ST2i64,            "st2",  ".d",     1, 0  },
-  { ARM64::ST2i8_POST,        "st2",  ".b",     1, 2  },
-  { ARM64::ST2i16_POST,       "st2",  ".h",     1, 4  },
-  { ARM64::ST2i32_POST,       "st2",  ".s",     1, 8  },
-  { ARM64::ST2i64_POST,       "st2",  ".d",     1, 16 },
-  { ARM64::ST2Twov16b,        "st2",  ".16b",   0, 0  },
-  { ARM64::ST2Twov8h,         "st2",  ".8h",    0, 0  },
-  { ARM64::ST2Twov4s,         "st2",  ".4s",    0, 0  },
-  { ARM64::ST2Twov2d,         "st2",  ".2d",    0, 0  },
-  { ARM64::ST2Twov8b,         "st2",  ".8b",    0, 0  },
-  { ARM64::ST2Twov4h,         "st2",  ".4h",    0, 0  },
-  { ARM64::ST2Twov2s,         "st2",  ".2s",    0, 0  },
-  { ARM64::ST2Twov16b_POST,   "st2",  ".16b",   0, 32 },
-  { ARM64::ST2Twov8h_POST,    "st2",  ".8h",    0, 32 },
-  { ARM64::ST2Twov4s_POST,    "st2",  ".4s",    0, 32 },
-  { ARM64::ST2Twov2d_POST,    "st2",  ".2d",    0, 32 },
-  { ARM64::ST2Twov8b_POST,    "st2",  ".8b",    0, 16 },
-  { ARM64::ST2Twov4h_POST,    "st2",  ".4h",    0, 16 },
-  { ARM64::ST2Twov2s_POST,    "st2",  ".2s",    0, 16 },
-  { ARM64::ST3i8,             "st3",  ".b",     1, 0  },
-  { ARM64::ST3i16,            "st3",  ".h",     1, 0  },
-  { ARM64::ST3i32,            "st3",  ".s",     1, 0  },
-  { ARM64::ST3i64,            "st3",  ".d",     1, 0  },
-  { ARM64::ST3i8_POST,        "st3",  ".b",     1, 3  },
-  { ARM64::ST3i16_POST,       "st3",  ".h",     1, 6  },
-  { ARM64::ST3i32_POST,       "st3",  ".s",     1, 12 },
-  { ARM64::ST3i64_POST,       "st3",  ".d",     1, 24 },
-  { ARM64::ST3Threev16b,      "st3",  ".16b",   0, 0  },
-  { ARM64::ST3Threev8h,       "st3",  ".8h",    0, 0  },
-  { ARM64::ST3Threev4s,       "st3",  ".4s",    0, 0  },
-  { ARM64::ST3Threev2d,       "st3",  ".2d",    0, 0  },
-  { ARM64::ST3Threev8b,       "st3",  ".8b",    0, 0  },
-  { ARM64::ST3Threev4h,       "st3",  ".4h",    0, 0  },
-  { ARM64::ST3Threev2s,       "st3",  ".2s",    0, 0  },
-  { ARM64::ST3Threev16b_POST, "st3",  ".16b",   0, 48 },
-  { ARM64::ST3Threev8h_POST,  "st3",  ".8h",    0, 48 },
-  { ARM64::ST3Threev4s_POST,  "st3",  ".4s",    0, 48 },
-  { ARM64::ST3Threev2d_POST,  "st3",  ".2d",    0, 48 },
-  { ARM64::ST3Threev8b_POST,  "st3",  ".8b",    0, 24 },
-  { ARM64::ST3Threev4h_POST,  "st3",  ".4h",    0, 24 },
-  { ARM64::ST3Threev2s_POST,  "st3",  ".2s",    0, 24 },
-  { ARM64::ST4i8,             "st4",  ".b",     1, 0  },
-  { ARM64::ST4i16,            "st4",  ".h",     1, 0  },
-  { ARM64::ST4i32,            "st4",  ".s",     1, 0  },
-  { ARM64::ST4i64,            "st4",  ".d",     1, 0  },
-  { ARM64::ST4i8_POST,        "st4",  ".b",     1, 4  },
-  { ARM64::ST4i16_POST,       "st4",  ".h",     1, 8  },
-  { ARM64::ST4i32_POST,       "st4",  ".s",     1, 16 },
-  { ARM64::ST4i64_POST,       "st4",  ".d",     1, 32 },
-  { ARM64::ST4Fourv16b,       "st4",  ".16b",   0, 0  },
-  { ARM64::ST4Fourv8h,        "st4",  ".8h",    0, 0  },
-  { ARM64::ST4Fourv4s,        "st4",  ".4s",    0, 0  },
-  { ARM64::ST4Fourv2d,        "st4",  ".2d",    0, 0  },
-  { ARM64::ST4Fourv8b,        "st4",  ".8b",    0, 0  },
-  { ARM64::ST4Fourv4h,        "st4",  ".4h",    0, 0  },
-  { ARM64::ST4Fourv2s,        "st4",  ".2s",    0, 0  },
-  { ARM64::ST4Fourv16b_POST,  "st4",  ".16b",   0, 64 },
-  { ARM64::ST4Fourv8h_POST,   "st4",  ".8h",    0, 64 },
-  { ARM64::ST4Fourv4s_POST,   "st4",  ".4s",    0, 64 },
-  { ARM64::ST4Fourv2d_POST,   "st4",  ".2d",    0, 64 },
-  { ARM64::ST4Fourv8b_POST,   "st4",  ".8b",    0, 32 },
-  { ARM64::ST4Fourv4h_POST,   "st4",  ".4h",    0, 32 },
-  { ARM64::ST4Fourv2s_POST,   "st4",  ".2s",    0, 32 },
+  { ARM64::LD1i8,             "ld1",  ".b",     1, true,  0  },
+  { ARM64::LD1i16,            "ld1",  ".h",     1, true,  0  },
+  { ARM64::LD1i32,            "ld1",  ".s",     1, true,  0  },
+  { ARM64::LD1i64,            "ld1",  ".d",     1, true,  0  },
+  { ARM64::LD1i8_POST,        "ld1",  ".b",     2, true,  1  },
+  { ARM64::LD1i16_POST,       "ld1",  ".h",     2, true,  2  },
+  { ARM64::LD1i32_POST,       "ld1",  ".s",     2, true,  4  },
+  { ARM64::LD1i64_POST,       "ld1",  ".d",     2, true,  8  },
+  { ARM64::LD1Rv16b,          "ld1r", ".16b",   0, false, 0  },
+  { ARM64::LD1Rv8h,           "ld1r", ".8h",    0, false, 0  },
+  { ARM64::LD1Rv4s,           "ld1r", ".4s",    0, false, 0  },
+  { ARM64::LD1Rv2d,           "ld1r", ".2d",    0, false, 0  },
+  { ARM64::LD1Rv8b,           "ld1r", ".8b",    0, false, 0  },
+  { ARM64::LD1Rv4h,           "ld1r", ".4h",    0, false, 0  },
+  { ARM64::LD1Rv2s,           "ld1r", ".2s",    0, false, 0  },
+  { ARM64::LD1Rv1d,           "ld1r", ".1d",    0, false, 0  },
+  { ARM64::LD1Rv16b_POST,     "ld1r", ".16b",   1, false, 1  },
+  { ARM64::LD1Rv8h_POST,      "ld1r", ".8h",    1, false, 2  },
+  { ARM64::LD1Rv4s_POST,      "ld1r", ".4s",    1, false, 4  },
+  { ARM64::LD1Rv2d_POST,      "ld1r", ".2d",    1, false, 8  },
+  { ARM64::LD1Rv8b_POST,      "ld1r", ".8b",    1, false, 1  },
+  { ARM64::LD1Rv4h_POST,      "ld1r", ".4h",    1, false, 2  },
+  { ARM64::LD1Rv2s_POST,      "ld1r", ".2s",    1, false, 4  },
+  { ARM64::LD1Rv1d_POST,      "ld1r", ".1d",    1, false, 8  },
+  { ARM64::LD1Onev16b,        "ld1",  ".16b",   0, false, 0  },
+  { ARM64::LD1Onev8h,         "ld1",  ".8h",    0, false, 0  },
+  { ARM64::LD1Onev4s,         "ld1",  ".4s",    0, false, 0  },
+  { ARM64::LD1Onev2d,         "ld1",  ".2d",    0, false, 0  },
+  { ARM64::LD1Onev8b,         "ld1",  ".8b",    0, false, 0  },
+  { ARM64::LD1Onev4h,         "ld1",  ".4h",    0, false, 0  },
+  { ARM64::LD1Onev2s,         "ld1",  ".2s",    0, false, 0  },
+  { ARM64::LD1Onev1d,         "ld1",  ".1d",    0, false, 0  },
+  { ARM64::LD1Onev16b_POST,   "ld1",  ".16b",   1, false, 16 },
+  { ARM64::LD1Onev8h_POST,    "ld1",  ".8h",    1, false, 16 },
+  { ARM64::LD1Onev4s_POST,    "ld1",  ".4s",    1, false, 16 },
+  { ARM64::LD1Onev2d_POST,    "ld1",  ".2d",    1, false, 16 },
+  { ARM64::LD1Onev8b_POST,    "ld1",  ".8b",    1, false, 8  },
+  { ARM64::LD1Onev4h_POST,    "ld1",  ".4h",    1, false, 8  },
+  { ARM64::LD1Onev2s_POST,    "ld1",  ".2s",    1, false, 8  },
+  { ARM64::LD1Onev1d_POST,    "ld1",  ".1d",    1, false, 8  },
+  { ARM64::LD1Twov16b,        "ld1",  ".16b",   0, false, 0  },
+  { ARM64::LD1Twov8h,         "ld1",  ".8h",    0, false, 0  },
+  { ARM64::LD1Twov4s,         "ld1",  ".4s",    0, false, 0  },
+  { ARM64::LD1Twov2d,         "ld1",  ".2d",    0, false, 0  },
+  { ARM64::LD1Twov8b,         "ld1",  ".8b",    0, false, 0  },
+  { ARM64::LD1Twov4h,         "ld1",  ".4h",    0, false, 0  },
+  { ARM64::LD1Twov2s,         "ld1",  ".2s",    0, false, 0  },
+  { ARM64::LD1Twov1d,         "ld1",  ".1d",    0, false, 0  },
+  { ARM64::LD1Twov16b_POST,   "ld1",  ".16b",   1, false, 32 },
+  { ARM64::LD1Twov8h_POST,    "ld1",  ".8h",    1, false, 32 },
+  { ARM64::LD1Twov4s_POST,    "ld1",  ".4s",    1, false, 32 },
+  { ARM64::LD1Twov2d_POST,    "ld1",  ".2d",    1, false, 32 },
+  { ARM64::LD1Twov8b_POST,    "ld1",  ".8b",    1, false, 16 },
+  { ARM64::LD1Twov4h_POST,    "ld1",  ".4h",    1, false, 16 },
+  { ARM64::LD1Twov2s_POST,    "ld1",  ".2s",    1, false, 16 },
+  { ARM64::LD1Twov1d_POST,    "ld1",  ".1d",    1, false, 16 },
+  { ARM64::LD1Threev16b,      "ld1",  ".16b",   0, false, 0  },
+  { ARM64::LD1Threev8h,       "ld1",  ".8h",    0, false, 0  },
+  { ARM64::LD1Threev4s,       "ld1",  ".4s",    0, false, 0  },
+  { ARM64::LD1Threev2d,       "ld1",  ".2d",    0, false, 0  },
+  { ARM64::LD1Threev8b,       "ld1",  ".8b",    0, false, 0  },
+  { ARM64::LD1Threev4h,       "ld1",  ".4h",    0, false, 0  },
+  { ARM64::LD1Threev2s,       "ld1",  ".2s",    0, false, 0  },
+  { ARM64::LD1Threev1d,       "ld1",  ".1d",    0, false, 0  },
+  { ARM64::LD1Threev16b_POST, "ld1",  ".16b",   1, false, 48 },
+  { ARM64::LD1Threev8h_POST,  "ld1",  ".8h",    1, false, 48 },
+  { ARM64::LD1Threev4s_POST,  "ld1",  ".4s",    1, false, 48 },
+  { ARM64::LD1Threev2d_POST,  "ld1",  ".2d",    1, false, 48 },
+  { ARM64::LD1Threev8b_POST,  "ld1",  ".8b",    1, false, 24 },
+  { ARM64::LD1Threev4h_POST,  "ld1",  ".4h",    1, false, 24 },
+  { ARM64::LD1Threev2s_POST,  "ld1",  ".2s",    1, false, 24 },
+  { ARM64::LD1Threev1d_POST,  "ld1",  ".1d",    1, false, 24 },
+  { ARM64::LD1Fourv16b,       "ld1",  ".16b",   0, false, 0  },
+  { ARM64::LD1Fourv8h,        "ld1",  ".8h",    0, false, 0  },
+  { ARM64::LD1Fourv4s,        "ld1",  ".4s",    0, false, 0  },
+  { ARM64::LD1Fourv2d,        "ld1",  ".2d",    0, false, 0  },
+  { ARM64::LD1Fourv8b,        "ld1",  ".8b",    0, false, 0  },
+  { ARM64::LD1Fourv4h,        "ld1",  ".4h",    0, false, 0  },
+  { ARM64::LD1Fourv2s,        "ld1",  ".2s",    0, false, 0  },
+  { ARM64::LD1Fourv1d,        "ld1",  ".1d",    0, false, 0  },
+  { ARM64::LD1Fourv16b_POST,  "ld1",  ".16b",   1, false, 64 },
+  { ARM64::LD1Fourv8h_POST,   "ld1",  ".8h",    1, false, 64 },
+  { ARM64::LD1Fourv4s_POST,   "ld1",  ".4s",    1, false, 64 },
+  { ARM64::LD1Fourv2d_POST,   "ld1",  ".2d",    1, false, 64 },
+  { ARM64::LD1Fourv8b_POST,   "ld1",  ".8b",    1, false, 32 },
+  { ARM64::LD1Fourv4h_POST,   "ld1",  ".4h",    1, false, 32 },
+  { ARM64::LD1Fourv2s_POST,   "ld1",  ".2s",    1, false, 32 },
+  { ARM64::LD1Fourv1d_POST,   "ld1",  ".1d",    1, false, 32 },
+  { ARM64::LD2i8,             "ld2",  ".b",     1, true,  0  },
+  { ARM64::LD2i16,            "ld2",  ".h",     1, true,  0  },
+  { ARM64::LD2i32,            "ld2",  ".s",     1, true,  0  },
+  { ARM64::LD2i64,            "ld2",  ".d",     1, true,  0  },
+  { ARM64::LD2i8_POST,        "ld2",  ".b",     2, true,  2  },
+  { ARM64::LD2i16_POST,       "ld2",  ".h",     2, true,  4  },
+  { ARM64::LD2i32_POST,       "ld2",  ".s",     2, true,  8  },
+  { ARM64::LD2i64_POST,       "ld2",  ".d",     2, true,  16  },
+  { ARM64::LD2Rv16b,          "ld2r", ".16b",   0, false, 0  },
+  { ARM64::LD2Rv8h,           "ld2r", ".8h",    0, false, 0  },
+  { ARM64::LD2Rv4s,           "ld2r", ".4s",    0, false, 0  },
+  { ARM64::LD2Rv2d,           "ld2r", ".2d",    0, false, 0  },
+  { ARM64::LD2Rv8b,           "ld2r", ".8b",    0, false, 0  },
+  { ARM64::LD2Rv4h,           "ld2r", ".4h",    0, false, 0  },
+  { ARM64::LD2Rv2s,           "ld2r", ".2s",    0, false, 0  },
+  { ARM64::LD2Rv1d,           "ld2r", ".1d",    0, false, 0  },
+  { ARM64::LD2Rv16b_POST,     "ld2r", ".16b",   1, false, 2  },
+  { ARM64::LD2Rv8h_POST,      "ld2r", ".8h",    1, false, 4  },
+  { ARM64::LD2Rv4s_POST,      "ld2r", ".4s",    1, false, 8  },
+  { ARM64::LD2Rv2d_POST,      "ld2r", ".2d",    1, false, 16 },
+  { ARM64::LD2Rv8b_POST,      "ld2r", ".8b",    1, false, 2  },
+  { ARM64::LD2Rv4h_POST,      "ld2r", ".4h",    1, false, 4  },
+  { ARM64::LD2Rv2s_POST,      "ld2r", ".2s",    1, false, 8  },
+  { ARM64::LD2Rv1d_POST,      "ld2r", ".1d",    1, false, 16 },
+  { ARM64::LD2Twov16b,        "ld2",  ".16b",   0, false, 0  },
+  { ARM64::LD2Twov8h,         "ld2",  ".8h",    0, false, 0  },
+  { ARM64::LD2Twov4s,         "ld2",  ".4s",    0, false, 0  },
+  { ARM64::LD2Twov2d,         "ld2",  ".2d",    0, false, 0  },
+  { ARM64::LD2Twov8b,         "ld2",  ".8b",    0, false, 0  },
+  { ARM64::LD2Twov4h,         "ld2",  ".4h",    0, false, 0  },
+  { ARM64::LD2Twov2s,         "ld2",  ".2s",    0, false, 0  },
+  { ARM64::LD2Twov16b_POST,   "ld2",  ".16b",   1, false, 32 },
+  { ARM64::LD2Twov8h_POST,    "ld2",  ".8h",    1, false, 32 },
+  { ARM64::LD2Twov4s_POST,    "ld2",  ".4s",    1, false, 32 },
+  { ARM64::LD2Twov2d_POST,    "ld2",  ".2d",    1, false, 32 },
+  { ARM64::LD2Twov8b_POST,    "ld2",  ".8b",    1, false, 16 },
+  { ARM64::LD2Twov4h_POST,    "ld2",  ".4h",    1, false, 16 },
+  { ARM64::LD2Twov2s_POST,    "ld2",  ".2s",    1, false, 16 },
+  { ARM64::LD3i8,             "ld3",  ".b",     1, true,  0  },
+  { ARM64::LD3i16,            "ld3",  ".h",     1, true,  0  },
+  { ARM64::LD3i32,            "ld3",  ".s",     1, true,  0  },
+  { ARM64::LD3i64,            "ld3",  ".d",     1, true,  0  },
+  { ARM64::LD3i8_POST,        "ld3",  ".b",     2, true,  3  },
+  { ARM64::LD3i16_POST,       "ld3",  ".h",     2, true,  6  },
+  { ARM64::LD3i32_POST,       "ld3",  ".s",     2, true,  12  },
+  { ARM64::LD3i64_POST,       "ld3",  ".d",     2, true,  24  },
+  { ARM64::LD3Rv16b,          "ld3r", ".16b",   0, false, 0  },
+  { ARM64::LD3Rv8h,           "ld3r", ".8h",    0, false, 0  },
+  { ARM64::LD3Rv4s,           "ld3r", ".4s",    0, false, 0  },
+  { ARM64::LD3Rv2d,           "ld3r", ".2d",    0, false, 0  },
+  { ARM64::LD3Rv8b,           "ld3r", ".8b",    0, false, 0  },
+  { ARM64::LD3Rv4h,           "ld3r", ".4h",    0, false, 0  },
+  { ARM64::LD3Rv2s,           "ld3r", ".2s",    0, false, 0  },
+  { ARM64::LD3Rv1d,           "ld3r", ".1d",    0, false, 0  },
+  { ARM64::LD3Rv16b_POST,     "ld3r", ".16b",   1, false, 3  },
+  { ARM64::LD3Rv8h_POST,      "ld3r", ".8h",    1, false, 6  },
+  { ARM64::LD3Rv4s_POST,      "ld3r", ".4s",    1, false, 12 },
+  { ARM64::LD3Rv2d_POST,      "ld3r", ".2d",    1, false, 24 },
+  { ARM64::LD3Rv8b_POST,      "ld3r", ".8b",    1, false, 3  },
+  { ARM64::LD3Rv4h_POST,      "ld3r", ".4h",    1, false, 6  },
+  { ARM64::LD3Rv2s_POST,      "ld3r", ".2s",    1, false, 12 },
+  { ARM64::LD3Rv1d_POST,      "ld3r", ".1d",    1, false, 24 },
+  { ARM64::LD3Threev16b,      "ld3",  ".16b",   0, false, 0  },
+  { ARM64::LD3Threev8h,       "ld3",  ".8h",    0, false, 0  },
+  { ARM64::LD3Threev4s,       "ld3",  ".4s",    0, false, 0  },
+  { ARM64::LD3Threev2d,       "ld3",  ".2d",    0, false, 0  },
+  { ARM64::LD3Threev8b,       "ld3",  ".8b",    0, false, 0  },
+  { ARM64::LD3Threev4h,       "ld3",  ".4h",    0, false, 0  },
+  { ARM64::LD3Threev2s,       "ld3",  ".2s",    0, false, 0  },
+  { ARM64::LD3Threev16b_POST, "ld3",  ".16b",   1, false, 48 },
+  { ARM64::LD3Threev8h_POST,  "ld3",  ".8h",    1, false, 48 },
+  { ARM64::LD3Threev4s_POST,  "ld3",  ".4s",    1, false, 48 },
+  { ARM64::LD3Threev2d_POST,  "ld3",  ".2d",    1, false, 48 },
+  { ARM64::LD3Threev8b_POST,  "ld3",  ".8b",    1, false, 24 },
+  { ARM64::LD3Threev4h_POST,  "ld3",  ".4h",    1, false, 24 },
+  { ARM64::LD3Threev2s_POST,  "ld3",  ".2s",    1, false, 24 },
+  { ARM64::LD4i8,             "ld4",  ".b",     1, true,  0  },
+  { ARM64::LD4i16,            "ld4",  ".h",     1, true,  0  },
+  { ARM64::LD4i32,            "ld4",  ".s",     1, true,  0  },
+  { ARM64::LD4i64,            "ld4",  ".d",     1, true,  0  },
+  { ARM64::LD4i8_POST,        "ld4",  ".b",     2, true,  4  },
+  { ARM64::LD4i16_POST,       "ld4",  ".h",     2, true,  8  },
+  { ARM64::LD4i32_POST,       "ld4",  ".s",     2, true,  16 },
+  { ARM64::LD4i64_POST,       "ld4",  ".d",     2, true,  32 },
+  { ARM64::LD4Rv16b,          "ld4r", ".16b",   0, false, 0  },
+  { ARM64::LD4Rv8h,           "ld4r", ".8h",    0, false, 0  },
+  { ARM64::LD4Rv4s,           "ld4r", ".4s",    0, false, 0  },
+  { ARM64::LD4Rv2d,           "ld4r", ".2d",    0, false, 0  },
+  { ARM64::LD4Rv8b,           "ld4r", ".8b",    0, false, 0  },
+  { ARM64::LD4Rv4h,           "ld4r", ".4h",    0, false, 0  },
+  { ARM64::LD4Rv2s,           "ld4r", ".2s",    0, false, 0  },
+  { ARM64::LD4Rv1d,           "ld4r", ".1d",    0, false, 0  },
+  { ARM64::LD4Rv16b_POST,     "ld4r", ".16b",   1, false, 4  },
+  { ARM64::LD4Rv8h_POST,      "ld4r", ".8h",    1, false, 8  },
+  { ARM64::LD4Rv4s_POST,      "ld4r", ".4s",    1, false, 16 },
+  { ARM64::LD4Rv2d_POST,      "ld4r", ".2d",    1, false, 32 },
+  { ARM64::LD4Rv8b_POST,      "ld4r", ".8b",    1, false, 4  },
+  { ARM64::LD4Rv4h_POST,      "ld4r", ".4h",    1, false, 8  },
+  { ARM64::LD4Rv2s_POST,      "ld4r", ".2s",    1, false, 16 },
+  { ARM64::LD4Rv1d_POST,      "ld4r", ".1d",    1, false, 32 },
+  { ARM64::LD4Fourv16b,       "ld4",  ".16b",   0, false, 0  },
+  { ARM64::LD4Fourv8h,        "ld4",  ".8h",    0, false, 0  },
+  { ARM64::LD4Fourv4s,        "ld4",  ".4s",    0, false, 0  },
+  { ARM64::LD4Fourv2d,        "ld4",  ".2d",    0, false, 0  },
+  { ARM64::LD4Fourv8b,        "ld4",  ".8b",    0, false, 0  },
+  { ARM64::LD4Fourv4h,        "ld4",  ".4h",    0, false, 0  },
+  { ARM64::LD4Fourv2s,        "ld4",  ".2s",    0, false, 0  },
+  { ARM64::LD4Fourv16b_POST,  "ld4",  ".16b",   1, false, 64 },
+  { ARM64::LD4Fourv8h_POST,   "ld4",  ".8h",    1, false, 64 },
+  { ARM64::LD4Fourv4s_POST,   "ld4",  ".4s",    1, false, 64 },
+  { ARM64::LD4Fourv2d_POST,   "ld4",  ".2d",    1, false, 64 },
+  { ARM64::LD4Fourv8b_POST,   "ld4",  ".8b",    1, false, 32 },
+  { ARM64::LD4Fourv4h_POST,   "ld4",  ".4h",    1, false, 32 },
+  { ARM64::LD4Fourv2s_POST,   "ld4",  ".2s",    1, false, 32 },
+  { ARM64::ST1i8,             "st1",  ".b",     0, true,  0  },
+  { ARM64::ST1i16,            "st1",  ".h",     0, true,  0  },
+  { ARM64::ST1i32,            "st1",  ".s",     0, true,  0  },
+  { ARM64::ST1i64,            "st1",  ".d",     0, true,  0  },
+  { ARM64::ST1i8_POST,        "st1",  ".b",     1, true,  1  },
+  { ARM64::ST1i16_POST,       "st1",  ".h",     1, true,  2  },
+  { ARM64::ST1i32_POST,       "st1",  ".s",     1, true,  4  },
+  { ARM64::ST1i64_POST,       "st1",  ".d",     1, true,  8  },
+  { ARM64::ST1Onev16b,        "st1",  ".16b",   0, false, 0  },
+  { ARM64::ST1Onev8h,         "st1",  ".8h",    0, false, 0  },
+  { ARM64::ST1Onev4s,         "st1",  ".4s",    0, false, 0  },
+  { ARM64::ST1Onev2d,         "st1",  ".2d",    0, false, 0  },
+  { ARM64::ST1Onev8b,         "st1",  ".8b",    0, false, 0  },
+  { ARM64::ST1Onev4h,         "st1",  ".4h",    0, false, 0  },
+  { ARM64::ST1Onev2s,         "st1",  ".2s",    0, false, 0  },
+  { ARM64::ST1Onev1d,         "st1",  ".1d",    0, false, 0  },
+  { ARM64::ST1Onev16b_POST,   "st1",  ".16b",   1, false, 16 },
+  { ARM64::ST1Onev8h_POST,    "st1",  ".8h",    1, false, 16 },
+  { ARM64::ST1Onev4s_POST,    "st1",  ".4s",    1, false, 16 },
+  { ARM64::ST1Onev2d_POST,    "st1",  ".2d",    1, false, 16 },
+  { ARM64::ST1Onev8b_POST,    "st1",  ".8b",    1, false, 8  },
+  { ARM64::ST1Onev4h_POST,    "st1",  ".4h",    1, false, 8  },
+  { ARM64::ST1Onev2s_POST,    "st1",  ".2s",    1, false, 8  },
+  { ARM64::ST1Onev1d_POST,    "st1",  ".1d",    1, false, 8  },
+  { ARM64::ST1Twov16b,        "st1",  ".16b",   0, false, 0  },
+  { ARM64::ST1Twov8h,         "st1",  ".8h",    0, false, 0  },
+  { ARM64::ST1Twov4s,         "st1",  ".4s",    0, false, 0  },
+  { ARM64::ST1Twov2d,         "st1",  ".2d",    0, false, 0  },
+  { ARM64::ST1Twov8b,         "st1",  ".8b",    0, false, 0  },
+  { ARM64::ST1Twov4h,         "st1",  ".4h",    0, false, 0  },
+  { ARM64::ST1Twov2s,         "st1",  ".2s",    0, false, 0  },
+  { ARM64::ST1Twov1d,         "st1",  ".1d",    0, false, 0  },
+  { ARM64::ST1Twov16b_POST,   "st1",  ".16b",   1, false, 32 },
+  { ARM64::ST1Twov8h_POST,    "st1",  ".8h",    1, false, 32 },
+  { ARM64::ST1Twov4s_POST,    "st1",  ".4s",    1, false, 32 },
+  { ARM64::ST1Twov2d_POST,    "st1",  ".2d",    1, false, 32 },
+  { ARM64::ST1Twov8b_POST,    "st1",  ".8b",    1, false, 16 },
+  { ARM64::ST1Twov4h_POST,    "st1",  ".4h",    1, false, 16 },
+  { ARM64::ST1Twov2s_POST,    "st1",  ".2s",    1, false, 16 },
+  { ARM64::ST1Twov1d_POST,    "st1",  ".1d",    1, false, 16 },
+  { ARM64::ST1Threev16b,      "st1",  ".16b",   0, false, 0  },
+  { ARM64::ST1Threev8h,       "st1",  ".8h",    0, false, 0  },
+  { ARM64::ST1Threev4s,       "st1",  ".4s",    0, false, 0  },
+  { ARM64::ST1Threev2d,       "st1",  ".2d",    0, false, 0  },
+  { ARM64::ST1Threev8b,       "st1",  ".8b",    0, false, 0  },
+  { ARM64::ST1Threev4h,       "st1",  ".4h",    0, false, 0  },
+  { ARM64::ST1Threev2s,       "st1",  ".2s",    0, false, 0  },
+  { ARM64::ST1Threev1d,       "st1",  ".1d",    0, false, 0  },
+  { ARM64::ST1Threev16b_POST, "st1",  ".16b",   1, false, 48 },
+  { ARM64::ST1Threev8h_POST,  "st1",  ".8h",    1, false, 48 },
+  { ARM64::ST1Threev4s_POST,  "st1",  ".4s",    1, false, 48 },
+  { ARM64::ST1Threev2d_POST,  "st1",  ".2d",    1, false, 48 },
+  { ARM64::ST1Threev8b_POST,  "st1",  ".8b",    1, false, 24 },
+  { ARM64::ST1Threev4h_POST,  "st1",  ".4h",    1, false, 24 },
+  { ARM64::ST1Threev2s_POST,  "st1",  ".2s",    1, false, 24 },
+  { ARM64::ST1Threev1d_POST,  "st1",  ".1d",    1, false, 24 },
+  { ARM64::ST1Fourv16b,       "st1",  ".16b",   0, false, 0  },
+  { ARM64::ST1Fourv8h,        "st1",  ".8h",    0, false, 0  },
+  { ARM64::ST1Fourv4s,        "st1",  ".4s",    0, false, 0  },
+  { ARM64::ST1Fourv2d,        "st1",  ".2d",    0, false, 0  },
+  { ARM64::ST1Fourv8b,        "st1",  ".8b",    0, false, 0  },
+  { ARM64::ST1Fourv4h,        "st1",  ".4h",    0, false, 0  },
+  { ARM64::ST1Fourv2s,        "st1",  ".2s",    0, false, 0  },
+  { ARM64::ST1Fourv1d,        "st1",  ".1d",    0, false, 0  },
+  { ARM64::ST1Fourv16b_POST,  "st1",  ".16b",   1, false, 64 },
+  { ARM64::ST1Fourv8h_POST,   "st1",  ".8h",    1, false, 64 },
+  { ARM64::ST1Fourv4s_POST,   "st1",  ".4s",    1, false, 64 },
+  { ARM64::ST1Fourv2d_POST,   "st1",  ".2d",    1, false, 64 },
+  { ARM64::ST1Fourv8b_POST,   "st1",  ".8b",    1, false, 32 },
+  { ARM64::ST1Fourv4h_POST,   "st1",  ".4h",    1, false, 32 },
+  { ARM64::ST1Fourv2s_POST,   "st1",  ".2s",    1, false, 32 },
+  { ARM64::ST1Fourv1d_POST,   "st1",  ".1d",    1, false, 32 },
+  { ARM64::ST2i8,             "st2",  ".b",     0, true,  0  },
+  { ARM64::ST2i16,            "st2",  ".h",     0, true,  0  },
+  { ARM64::ST2i32,            "st2",  ".s",     0, true,  0  },
+  { ARM64::ST2i64,            "st2",  ".d",     0, true,  0  },
+  { ARM64::ST2i8_POST,        "st2",  ".b",     1, true,  2  },
+  { ARM64::ST2i16_POST,       "st2",  ".h",     1, true,  4  },
+  { ARM64::ST2i32_POST,       "st2",  ".s",     1, true,  8  },
+  { ARM64::ST2i64_POST,       "st2",  ".d",     1, true,  16 },
+  { ARM64::ST2Twov16b,        "st2",  ".16b",   0, false, 0  },
+  { ARM64::ST2Twov8h,         "st2",  ".8h",    0, false, 0  },
+  { ARM64::ST2Twov4s,         "st2",  ".4s",    0, false, 0  },
+  { ARM64::ST2Twov2d,         "st2",  ".2d",    0, false, 0  },
+  { ARM64::ST2Twov8b,         "st2",  ".8b",    0, false, 0  },
+  { ARM64::ST2Twov4h,         "st2",  ".4h",    0, false, 0  },
+  { ARM64::ST2Twov2s,         "st2",  ".2s",    0, false, 0  },
+  { ARM64::ST2Twov16b_POST,   "st2",  ".16b",   1, false, 32 },
+  { ARM64::ST2Twov8h_POST,    "st2",  ".8h",    1, false, 32 },
+  { ARM64::ST2Twov4s_POST,    "st2",  ".4s",    1, false, 32 },
+  { ARM64::ST2Twov2d_POST,    "st2",  ".2d",    1, false, 32 },
+  { ARM64::ST2Twov8b_POST,    "st2",  ".8b",    1, false, 16 },
+  { ARM64::ST2Twov4h_POST,    "st2",  ".4h",    1, false, 16 },
+  { ARM64::ST2Twov2s_POST,    "st2",  ".2s",    1, false, 16 },
+  { ARM64::ST3i8,             "st3",  ".b",     0, true,  0  },
+  { ARM64::ST3i16,            "st3",  ".h",     0, true,  0  },
+  { ARM64::ST3i32,            "st3",  ".s",     0, true,  0  },
+  { ARM64::ST3i64,            "st3",  ".d",     0, true,  0  },
+  { ARM64::ST3i8_POST,        "st3",  ".b",     1, true,  3  },
+  { ARM64::ST3i16_POST,       "st3",  ".h",     1, true,  6  },
+  { ARM64::ST3i32_POST,       "st3",  ".s",     1, true,  12 },
+  { ARM64::ST3i64_POST,       "st3",  ".d",     1, true,  24 },
+  { ARM64::ST3Threev16b,      "st3",  ".16b",   0, false, 0  },
+  { ARM64::ST3Threev8h,       "st3",  ".8h",    0, false, 0  },
+  { ARM64::ST3Threev4s,       "st3",  ".4s",    0, false, 0  },
+  { ARM64::ST3Threev2d,       "st3",  ".2d",    0, false, 0  },
+  { ARM64::ST3Threev8b,       "st3",  ".8b",    0, false, 0  },
+  { ARM64::ST3Threev4h,       "st3",  ".4h",    0, false, 0  },
+  { ARM64::ST3Threev2s,       "st3",  ".2s",    0, false, 0  },
+  { ARM64::ST3Threev16b_POST, "st3",  ".16b",   1, false, 48 },
+  { ARM64::ST3Threev8h_POST,  "st3",  ".8h",    1, false, 48 },
+  { ARM64::ST3Threev4s_POST,  "st3",  ".4s",    1, false, 48 },
+  { ARM64::ST3Threev2d_POST,  "st3",  ".2d",    1, false, 48 },
+  { ARM64::ST3Threev8b_POST,  "st3",  ".8b",    1, false, 24 },
+  { ARM64::ST3Threev4h_POST,  "st3",  ".4h",    1, false, 24 },
+  { ARM64::ST3Threev2s_POST,  "st3",  ".2s",    1, false, 24 },
+  { ARM64::ST4i8,             "st4",  ".b",     0, true,  0  },
+  { ARM64::ST4i16,            "st4",  ".h",     0, true,  0  },
+  { ARM64::ST4i32,            "st4",  ".s",     0, true,  0  },
+  { ARM64::ST4i64,            "st4",  ".d",     0, true,  0  },
+  { ARM64::ST4i8_POST,        "st4",  ".b",     1, true,  4  },
+  { ARM64::ST4i16_POST,       "st4",  ".h",     1, true,  8  },
+  { ARM64::ST4i32_POST,       "st4",  ".s",     1, true,  16 },
+  { ARM64::ST4i64_POST,       "st4",  ".d",     1, true,  32 },
+  { ARM64::ST4Fourv16b,       "st4",  ".16b",   0, false, 0  },
+  { ARM64::ST4Fourv8h,        "st4",  ".8h",    0, false, 0  },
+  { ARM64::ST4Fourv4s,        "st4",  ".4s",    0, false, 0  },
+  { ARM64::ST4Fourv2d,        "st4",  ".2d",    0, false, 0  },
+  { ARM64::ST4Fourv8b,        "st4",  ".8b",    0, false, 0  },
+  { ARM64::ST4Fourv4h,        "st4",  ".4h",    0, false, 0  },
+  { ARM64::ST4Fourv2s,        "st4",  ".2s",    0, false, 0  },
+  { ARM64::ST4Fourv16b_POST,  "st4",  ".16b",   1, false, 64 },
+  { ARM64::ST4Fourv8h_POST,   "st4",  ".8h",    1, false, 64 },
+  { ARM64::ST4Fourv4s_POST,   "st4",  ".4s",    1, false, 64 },
+  { ARM64::ST4Fourv2d_POST,   "st4",  ".2d",    1, false, 64 },
+  { ARM64::ST4Fourv8b_POST,   "st4",  ".8b",    1, false, 32 },
+  { ARM64::ST4Fourv4h_POST,   "st4",  ".4h",    1, false, 32 },
+  { ARM64::ST4Fourv2s_POST,   "st4",  ".2s",    1, false, 32 },
 };
 
 static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
@@ -770,19 +771,19 @@ void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
 
     // Now onto the operands: first a vector list with possible lane
     // specifier. E.g. { v0 }[2]
-    printVectorList(MI, 0, O, "");
+    int OpNum = LdStDesc->ListOperand;
+    printVectorList(MI, OpNum++, O, "");
 
-    if (LdStDesc->LaneOperand != 0)
-      O << '[' << MI->getOperand(LdStDesc->LaneOperand).getImm() << ']';
+    if (LdStDesc->HasLane)
+      O << '[' << MI->getOperand(OpNum++).getImm() << ']';
 
     // Next the address: [xN]
-    unsigned AddrOpNum = LdStDesc->LaneOperand + 1;
-    unsigned AddrReg = MI->getOperand(AddrOpNum).getReg();
+    unsigned AddrReg = MI->getOperand(OpNum++).getReg();
     O << ", [" << getRegisterName(AddrReg) << ']';
 
     // Finally, there might be a post-indexed offset.
     if (LdStDesc->NaturalOffset != 0) {
-      unsigned Reg = MI->getOperand(AddrOpNum + 1).getReg();
+      unsigned Reg = MI->getOperand(OpNum++).getReg();
       if (Reg != ARM64::XZR)
         O << ", " << getRegisterName(Reg);
       else {