mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-10 02:17:46 +00:00
ARM64: refactor NEON post-indexed loads & stores (MC).
Previously, LLVM had no knowledge that these instructions actually modified their address register: fine if they never end up in CodeGen, but when I'd rather like to write some patterns for them it becomes a disaster. The change is mostly straightforward, I think the most significant design decision was to *always* put the address write-back first. This allows loads and stores to be accessed more uniformly, for example permitting the continued sharing of the InstAlias definitions. I also discovered that the custom Decode logic is no longer needed, so I removed it. No tests, because there should be no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207839 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
@@ -143,13 +143,6 @@ static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
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const void *Decoder);
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static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSIMDLdStPost(llvm::MCInst &Inst, uint32_t insn,
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uint64_t Addr, const void *Decoder);
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static DecodeStatus DecodeSIMDLdStSingle(llvm::MCInst &Inst, uint32_t insn,
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uint64_t Addr, const void *Decoder);
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static DecodeStatus DecodeSIMDLdStSingleTied(llvm::MCInst &Inst, uint32_t insn,
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uint64_t Addr,
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const void *Decoder);
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static DecodeStatus DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder);
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@@ -1455,567 +1448,3 @@ static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
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return Success;
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}
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static DecodeStatus DecodeSIMDLdStPost(llvm::MCInst &Inst, uint32_t insn,
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uint64_t Addr, const void *Decoder) {
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uint64_t Rd = fieldFromInstruction(insn, 0, 5);
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uint64_t Rn = fieldFromInstruction(insn, 5, 5);
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uint64_t Rm = fieldFromInstruction(insn, 16, 5);
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switch (Inst.getOpcode()) {
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default:
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return Fail;
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case ARM64::ST1Onev8b_POST:
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case ARM64::ST1Onev4h_POST:
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case ARM64::ST1Onev2s_POST:
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case ARM64::ST1Onev1d_POST:
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case ARM64::LD1Onev8b_POST:
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case ARM64::LD1Onev4h_POST:
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case ARM64::LD1Onev2s_POST:
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case ARM64::LD1Onev1d_POST:
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DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
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break;
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case ARM64::ST1Onev16b_POST:
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case ARM64::ST1Onev8h_POST:
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case ARM64::ST1Onev4s_POST:
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case ARM64::ST1Onev2d_POST:
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case ARM64::LD1Onev16b_POST:
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case ARM64::LD1Onev8h_POST:
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case ARM64::LD1Onev4s_POST:
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case ARM64::LD1Onev2d_POST:
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DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
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break;
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case ARM64::ST1Twov8b_POST:
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case ARM64::ST1Twov4h_POST:
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case ARM64::ST1Twov2s_POST:
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case ARM64::ST1Twov1d_POST:
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case ARM64::ST2Twov8b_POST:
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case ARM64::ST2Twov4h_POST:
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case ARM64::ST2Twov2s_POST:
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case ARM64::LD1Twov8b_POST:
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case ARM64::LD1Twov4h_POST:
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case ARM64::LD1Twov2s_POST:
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case ARM64::LD1Twov1d_POST:
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case ARM64::LD2Twov8b_POST:
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case ARM64::LD2Twov4h_POST:
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case ARM64::LD2Twov2s_POST:
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DecodeDDRegisterClass(Inst, Rd, Addr, Decoder);
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break;
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case ARM64::ST1Threev8b_POST:
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case ARM64::ST1Threev4h_POST:
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case ARM64::ST1Threev2s_POST:
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case ARM64::ST1Threev1d_POST:
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case ARM64::ST3Threev8b_POST:
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case ARM64::ST3Threev4h_POST:
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case ARM64::ST3Threev2s_POST:
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case ARM64::LD1Threev8b_POST:
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case ARM64::LD1Threev4h_POST:
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case ARM64::LD1Threev2s_POST:
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case ARM64::LD1Threev1d_POST:
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case ARM64::LD3Threev8b_POST:
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case ARM64::LD3Threev4h_POST:
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case ARM64::LD3Threev2s_POST:
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DecodeDDDRegisterClass(Inst, Rd, Addr, Decoder);
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break;
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case ARM64::ST1Fourv8b_POST:
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case ARM64::ST1Fourv4h_POST:
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case ARM64::ST1Fourv2s_POST:
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case ARM64::ST1Fourv1d_POST:
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case ARM64::ST4Fourv8b_POST:
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case ARM64::ST4Fourv4h_POST:
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case ARM64::ST4Fourv2s_POST:
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case ARM64::LD1Fourv8b_POST:
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case ARM64::LD1Fourv4h_POST:
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case ARM64::LD1Fourv2s_POST:
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case ARM64::LD1Fourv1d_POST:
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case ARM64::LD4Fourv8b_POST:
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case ARM64::LD4Fourv4h_POST:
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case ARM64::LD4Fourv2s_POST:
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DecodeDDDDRegisterClass(Inst, Rd, Addr, Decoder);
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break;
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case ARM64::ST1Twov16b_POST:
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case ARM64::ST1Twov8h_POST:
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case ARM64::ST1Twov4s_POST:
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case ARM64::ST1Twov2d_POST:
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case ARM64::ST2Twov16b_POST:
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case ARM64::ST2Twov8h_POST:
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case ARM64::ST2Twov4s_POST:
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case ARM64::ST2Twov2d_POST:
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case ARM64::LD1Twov16b_POST:
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case ARM64::LD1Twov8h_POST:
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case ARM64::LD1Twov4s_POST:
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case ARM64::LD1Twov2d_POST:
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case ARM64::LD2Twov16b_POST:
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case ARM64::LD2Twov8h_POST:
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case ARM64::LD2Twov4s_POST:
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case ARM64::LD2Twov2d_POST:
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DecodeQQRegisterClass(Inst, Rd, Addr, Decoder);
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break;
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case ARM64::ST1Threev16b_POST:
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case ARM64::ST1Threev8h_POST:
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case ARM64::ST1Threev4s_POST:
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case ARM64::ST1Threev2d_POST:
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case ARM64::ST3Threev16b_POST:
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case ARM64::ST3Threev8h_POST:
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case ARM64::ST3Threev4s_POST:
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case ARM64::ST3Threev2d_POST:
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case ARM64::LD1Threev16b_POST:
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case ARM64::LD1Threev8h_POST:
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case ARM64::LD1Threev4s_POST:
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case ARM64::LD1Threev2d_POST:
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case ARM64::LD3Threev16b_POST:
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case ARM64::LD3Threev8h_POST:
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case ARM64::LD3Threev4s_POST:
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case ARM64::LD3Threev2d_POST:
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DecodeQQQRegisterClass(Inst, Rd, Addr, Decoder);
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break;
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case ARM64::ST1Fourv16b_POST:
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case ARM64::ST1Fourv8h_POST:
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case ARM64::ST1Fourv4s_POST:
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case ARM64::ST1Fourv2d_POST:
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case ARM64::ST4Fourv16b_POST:
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case ARM64::ST4Fourv8h_POST:
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case ARM64::ST4Fourv4s_POST:
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case ARM64::ST4Fourv2d_POST:
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case ARM64::LD1Fourv16b_POST:
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case ARM64::LD1Fourv8h_POST:
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case ARM64::LD1Fourv4s_POST:
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case ARM64::LD1Fourv2d_POST:
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case ARM64::LD4Fourv16b_POST:
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case ARM64::LD4Fourv8h_POST:
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case ARM64::LD4Fourv4s_POST:
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case ARM64::LD4Fourv2d_POST:
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DecodeQQQQRegisterClass(Inst, Rd, Addr, Decoder);
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break;
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}
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DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
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DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
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return Success;
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}
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static DecodeStatus DecodeSIMDLdStSingle(llvm::MCInst &Inst, uint32_t insn,
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uint64_t Addr, const void *Decoder) {
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uint64_t Rt = fieldFromInstruction(insn, 0, 5);
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uint64_t Rn = fieldFromInstruction(insn, 5, 5);
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uint64_t Rm = fieldFromInstruction(insn, 16, 5);
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uint64_t size = fieldFromInstruction(insn, 10, 2);
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uint64_t S = fieldFromInstruction(insn, 12, 1);
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uint64_t Q = fieldFromInstruction(insn, 30, 1);
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uint64_t index = 0;
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switch (Inst.getOpcode()) {
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case ARM64::ST1i8:
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case ARM64::ST1i8_POST:
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case ARM64::ST2i8:
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case ARM64::ST2i8_POST:
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case ARM64::ST3i8_POST:
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case ARM64::ST3i8:
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case ARM64::ST4i8_POST:
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case ARM64::ST4i8:
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index = (Q << 3) | (S << 2) | size;
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break;
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case ARM64::ST1i16:
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case ARM64::ST1i16_POST:
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case ARM64::ST2i16:
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case ARM64::ST2i16_POST:
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case ARM64::ST3i16_POST:
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case ARM64::ST3i16:
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case ARM64::ST4i16_POST:
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case ARM64::ST4i16:
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index = (Q << 2) | (S << 1) | (size >> 1);
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break;
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case ARM64::ST1i32:
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case ARM64::ST1i32_POST:
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case ARM64::ST2i32:
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case ARM64::ST2i32_POST:
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case ARM64::ST3i32_POST:
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case ARM64::ST3i32:
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case ARM64::ST4i32_POST:
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case ARM64::ST4i32:
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index = (Q << 1) | S;
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break;
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case ARM64::ST1i64:
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case ARM64::ST1i64_POST:
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case ARM64::ST2i64:
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case ARM64::ST2i64_POST:
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case ARM64::ST3i64_POST:
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case ARM64::ST3i64:
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case ARM64::ST4i64_POST:
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case ARM64::ST4i64:
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index = Q;
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break;
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}
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switch (Inst.getOpcode()) {
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default:
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return Fail;
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case ARM64::LD1Rv8b:
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case ARM64::LD1Rv8b_POST:
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case ARM64::LD1Rv4h:
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case ARM64::LD1Rv4h_POST:
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case ARM64::LD1Rv2s:
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case ARM64::LD1Rv2s_POST:
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case ARM64::LD1Rv1d:
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case ARM64::LD1Rv1d_POST:
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DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
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break;
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case ARM64::LD1Rv16b:
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case ARM64::LD1Rv16b_POST:
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case ARM64::LD1Rv8h:
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case ARM64::LD1Rv8h_POST:
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case ARM64::LD1Rv4s:
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case ARM64::LD1Rv4s_POST:
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case ARM64::LD1Rv2d:
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case ARM64::LD1Rv2d_POST:
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case ARM64::ST1i8:
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case ARM64::ST1i8_POST:
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case ARM64::ST1i16:
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case ARM64::ST1i16_POST:
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case ARM64::ST1i32:
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case ARM64::ST1i32_POST:
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case ARM64::ST1i64:
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case ARM64::ST1i64_POST:
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DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
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break;
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case ARM64::LD2Rv16b:
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case ARM64::LD2Rv16b_POST:
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case ARM64::LD2Rv8h:
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case ARM64::LD2Rv8h_POST:
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case ARM64::LD2Rv4s:
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case ARM64::LD2Rv4s_POST:
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case ARM64::LD2Rv2d:
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case ARM64::LD2Rv2d_POST:
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case ARM64::ST2i8:
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case ARM64::ST2i8_POST:
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case ARM64::ST2i16:
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case ARM64::ST2i16_POST:
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case ARM64::ST2i32:
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case ARM64::ST2i32_POST:
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case ARM64::ST2i64:
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case ARM64::ST2i64_POST:
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DecodeQQRegisterClass(Inst, Rt, Addr, Decoder);
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break;
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case ARM64::LD2Rv8b:
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case ARM64::LD2Rv8b_POST:
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case ARM64::LD2Rv4h:
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case ARM64::LD2Rv4h_POST:
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case ARM64::LD2Rv2s:
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case ARM64::LD2Rv2s_POST:
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case ARM64::LD2Rv1d:
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case ARM64::LD2Rv1d_POST:
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DecodeDDRegisterClass(Inst, Rt, Addr, Decoder);
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break;
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case ARM64::LD3Rv8b:
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case ARM64::LD3Rv8b_POST:
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case ARM64::LD3Rv4h:
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case ARM64::LD3Rv4h_POST:
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case ARM64::LD3Rv2s:
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case ARM64::LD3Rv2s_POST:
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case ARM64::LD3Rv1d:
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case ARM64::LD3Rv1d_POST:
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DecodeDDDRegisterClass(Inst, Rt, Addr, Decoder);
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break;
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case ARM64::LD3Rv16b:
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case ARM64::LD3Rv16b_POST:
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case ARM64::LD3Rv8h:
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case ARM64::LD3Rv8h_POST:
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case ARM64::LD3Rv4s:
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case ARM64::LD3Rv4s_POST:
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case ARM64::LD3Rv2d:
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case ARM64::LD3Rv2d_POST:
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case ARM64::ST3i8:
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case ARM64::ST3i8_POST:
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case ARM64::ST3i16:
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case ARM64::ST3i16_POST:
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case ARM64::ST3i32:
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case ARM64::ST3i32_POST:
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case ARM64::ST3i64:
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case ARM64::ST3i64_POST:
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DecodeQQQRegisterClass(Inst, Rt, Addr, Decoder);
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break;
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case ARM64::LD4Rv8b:
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case ARM64::LD4Rv8b_POST:
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case ARM64::LD4Rv4h:
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case ARM64::LD4Rv4h_POST:
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case ARM64::LD4Rv2s:
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case ARM64::LD4Rv2s_POST:
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case ARM64::LD4Rv1d:
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case ARM64::LD4Rv1d_POST:
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DecodeDDDDRegisterClass(Inst, Rt, Addr, Decoder);
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break;
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case ARM64::LD4Rv16b:
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case ARM64::LD4Rv16b_POST:
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case ARM64::LD4Rv8h:
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case ARM64::LD4Rv8h_POST:
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case ARM64::LD4Rv4s:
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case ARM64::LD4Rv4s_POST:
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case ARM64::LD4Rv2d:
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case ARM64::LD4Rv2d_POST:
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case ARM64::ST4i8:
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case ARM64::ST4i8_POST:
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case ARM64::ST4i16:
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case ARM64::ST4i16_POST:
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case ARM64::ST4i32:
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case ARM64::ST4i32_POST:
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case ARM64::ST4i64:
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case ARM64::ST4i64_POST:
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DecodeQQQQRegisterClass(Inst, Rt, Addr, Decoder);
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||||
break;
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||||
}
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switch (Inst.getOpcode()) {
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case ARM64::LD1Rv8b:
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case ARM64::LD1Rv8b_POST:
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case ARM64::LD1Rv16b:
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case ARM64::LD1Rv16b_POST:
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case ARM64::LD1Rv4h:
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case ARM64::LD1Rv4h_POST:
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case ARM64::LD1Rv8h:
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case ARM64::LD1Rv8h_POST:
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case ARM64::LD1Rv4s:
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||||
case ARM64::LD1Rv4s_POST:
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case ARM64::LD1Rv2s:
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||||
case ARM64::LD1Rv2s_POST:
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case ARM64::LD1Rv1d:
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||||
case ARM64::LD1Rv1d_POST:
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case ARM64::LD1Rv2d:
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||||
case ARM64::LD1Rv2d_POST:
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case ARM64::LD2Rv8b:
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||||
case ARM64::LD2Rv8b_POST:
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case ARM64::LD2Rv16b:
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||||
case ARM64::LD2Rv16b_POST:
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case ARM64::LD2Rv4h:
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case ARM64::LD2Rv4h_POST:
|
||||
case ARM64::LD2Rv8h:
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||||
case ARM64::LD2Rv8h_POST:
|
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case ARM64::LD2Rv2s:
|
||||
case ARM64::LD2Rv2s_POST:
|
||||
case ARM64::LD2Rv4s:
|
||||
case ARM64::LD2Rv4s_POST:
|
||||
case ARM64::LD2Rv2d:
|
||||
case ARM64::LD2Rv2d_POST:
|
||||
case ARM64::LD2Rv1d:
|
||||
case ARM64::LD2Rv1d_POST:
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||||
case ARM64::LD3Rv8b:
|
||||
case ARM64::LD3Rv8b_POST:
|
||||
case ARM64::LD3Rv16b:
|
||||
case ARM64::LD3Rv16b_POST:
|
||||
case ARM64::LD3Rv4h:
|
||||
case ARM64::LD3Rv4h_POST:
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||||
case ARM64::LD3Rv8h:
|
||||
case ARM64::LD3Rv8h_POST:
|
||||
case ARM64::LD3Rv2s:
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||||
case ARM64::LD3Rv2s_POST:
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||||
case ARM64::LD3Rv4s:
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||||
case ARM64::LD3Rv4s_POST:
|
||||
case ARM64::LD3Rv2d:
|
||||
case ARM64::LD3Rv2d_POST:
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||||
case ARM64::LD3Rv1d:
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||||
case ARM64::LD3Rv1d_POST:
|
||||
case ARM64::LD4Rv8b:
|
||||
case ARM64::LD4Rv8b_POST:
|
||||
case ARM64::LD4Rv16b:
|
||||
case ARM64::LD4Rv16b_POST:
|
||||
case ARM64::LD4Rv4h:
|
||||
case ARM64::LD4Rv4h_POST:
|
||||
case ARM64::LD4Rv8h:
|
||||
case ARM64::LD4Rv8h_POST:
|
||||
case ARM64::LD4Rv2s:
|
||||
case ARM64::LD4Rv2s_POST:
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||||
case ARM64::LD4Rv4s:
|
||||
case ARM64::LD4Rv4s_POST:
|
||||
case ARM64::LD4Rv2d:
|
||||
case ARM64::LD4Rv2d_POST:
|
||||
case ARM64::LD4Rv1d:
|
||||
case ARM64::LD4Rv1d_POST:
|
||||
break;
|
||||
default:
|
||||
Inst.addOperand(MCOperand::CreateImm(index));
|
||||
}
|
||||
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
|
||||
switch (Inst.getOpcode()) {
|
||||
case ARM64::ST1i8_POST:
|
||||
case ARM64::ST1i16_POST:
|
||||
case ARM64::ST1i32_POST:
|
||||
case ARM64::ST1i64_POST:
|
||||
case ARM64::LD1Rv8b_POST:
|
||||
case ARM64::LD1Rv16b_POST:
|
||||
case ARM64::LD1Rv4h_POST:
|
||||
case ARM64::LD1Rv8h_POST:
|
||||
case ARM64::LD1Rv2s_POST:
|
||||
case ARM64::LD1Rv4s_POST:
|
||||
case ARM64::LD1Rv1d_POST:
|
||||
case ARM64::LD1Rv2d_POST:
|
||||
case ARM64::ST2i8_POST:
|
||||
case ARM64::ST2i16_POST:
|
||||
case ARM64::ST2i32_POST:
|
||||
case ARM64::ST2i64_POST:
|
||||
case ARM64::LD2Rv8b_POST:
|
||||
case ARM64::LD2Rv16b_POST:
|
||||
case ARM64::LD2Rv4h_POST:
|
||||
case ARM64::LD2Rv8h_POST:
|
||||
case ARM64::LD2Rv2s_POST:
|
||||
case ARM64::LD2Rv4s_POST:
|
||||
case ARM64::LD2Rv2d_POST:
|
||||
case ARM64::LD2Rv1d_POST:
|
||||
case ARM64::ST3i8_POST:
|
||||
case ARM64::ST3i16_POST:
|
||||
case ARM64::ST3i32_POST:
|
||||
case ARM64::ST3i64_POST:
|
||||
case ARM64::LD3Rv8b_POST:
|
||||
case ARM64::LD3Rv16b_POST:
|
||||
case ARM64::LD3Rv4h_POST:
|
||||
case ARM64::LD3Rv8h_POST:
|
||||
case ARM64::LD3Rv2s_POST:
|
||||
case ARM64::LD3Rv4s_POST:
|
||||
case ARM64::LD3Rv2d_POST:
|
||||
case ARM64::LD3Rv1d_POST:
|
||||
case ARM64::ST4i8_POST:
|
||||
case ARM64::ST4i16_POST:
|
||||
case ARM64::ST4i32_POST:
|
||||
case ARM64::ST4i64_POST:
|
||||
case ARM64::LD4Rv8b_POST:
|
||||
case ARM64::LD4Rv16b_POST:
|
||||
case ARM64::LD4Rv4h_POST:
|
||||
case ARM64::LD4Rv8h_POST:
|
||||
case ARM64::LD4Rv2s_POST:
|
||||
case ARM64::LD4Rv4s_POST:
|
||||
case ARM64::LD4Rv2d_POST:
|
||||
case ARM64::LD4Rv1d_POST:
|
||||
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
}
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSIMDLdStSingleTied(llvm::MCInst &Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
const void *Decoder) {
|
||||
uint64_t Rt = fieldFromInstruction(insn, 0, 5);
|
||||
uint64_t Rn = fieldFromInstruction(insn, 5, 5);
|
||||
uint64_t Rm = fieldFromInstruction(insn, 16, 5);
|
||||
uint64_t size = fieldFromInstruction(insn, 10, 2);
|
||||
uint64_t S = fieldFromInstruction(insn, 12, 1);
|
||||
uint64_t Q = fieldFromInstruction(insn, 30, 1);
|
||||
uint64_t index = 0;
|
||||
|
||||
switch (Inst.getOpcode()) {
|
||||
case ARM64::LD1i8:
|
||||
case ARM64::LD1i8_POST:
|
||||
case ARM64::LD2i8:
|
||||
case ARM64::LD2i8_POST:
|
||||
case ARM64::LD3i8_POST:
|
||||
case ARM64::LD3i8:
|
||||
case ARM64::LD4i8_POST:
|
||||
case ARM64::LD4i8:
|
||||
index = (Q << 3) | (S << 2) | size;
|
||||
break;
|
||||
case ARM64::LD1i16:
|
||||
case ARM64::LD1i16_POST:
|
||||
case ARM64::LD2i16:
|
||||
case ARM64::LD2i16_POST:
|
||||
case ARM64::LD3i16_POST:
|
||||
case ARM64::LD3i16:
|
||||
case ARM64::LD4i16_POST:
|
||||
case ARM64::LD4i16:
|
||||
index = (Q << 2) | (S << 1) | (size >> 1);
|
||||
break;
|
||||
case ARM64::LD1i32:
|
||||
case ARM64::LD1i32_POST:
|
||||
case ARM64::LD2i32:
|
||||
case ARM64::LD2i32_POST:
|
||||
case ARM64::LD3i32_POST:
|
||||
case ARM64::LD3i32:
|
||||
case ARM64::LD4i32_POST:
|
||||
case ARM64::LD4i32:
|
||||
index = (Q << 1) | S;
|
||||
break;
|
||||
case ARM64::LD1i64:
|
||||
case ARM64::LD1i64_POST:
|
||||
case ARM64::LD2i64:
|
||||
case ARM64::LD2i64_POST:
|
||||
case ARM64::LD3i64_POST:
|
||||
case ARM64::LD3i64:
|
||||
case ARM64::LD4i64_POST:
|
||||
case ARM64::LD4i64:
|
||||
index = Q;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (Inst.getOpcode()) {
|
||||
default:
|
||||
return Fail;
|
||||
case ARM64::LD1i8:
|
||||
case ARM64::LD1i8_POST:
|
||||
case ARM64::LD1i16:
|
||||
case ARM64::LD1i16_POST:
|
||||
case ARM64::LD1i32:
|
||||
case ARM64::LD1i32_POST:
|
||||
case ARM64::LD1i64:
|
||||
case ARM64::LD1i64_POST:
|
||||
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
|
||||
DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
|
||||
break;
|
||||
case ARM64::LD2i8:
|
||||
case ARM64::LD2i8_POST:
|
||||
case ARM64::LD2i16:
|
||||
case ARM64::LD2i16_POST:
|
||||
case ARM64::LD2i32:
|
||||
case ARM64::LD2i32_POST:
|
||||
case ARM64::LD2i64:
|
||||
case ARM64::LD2i64_POST:
|
||||
DecodeQQRegisterClass(Inst, Rt, Addr, Decoder);
|
||||
DecodeQQRegisterClass(Inst, Rt, Addr, Decoder);
|
||||
break;
|
||||
case ARM64::LD3i8:
|
||||
case ARM64::LD3i8_POST:
|
||||
case ARM64::LD3i16:
|
||||
case ARM64::LD3i16_POST:
|
||||
case ARM64::LD3i32:
|
||||
case ARM64::LD3i32_POST:
|
||||
case ARM64::LD3i64:
|
||||
case ARM64::LD3i64_POST:
|
||||
DecodeQQQRegisterClass(Inst, Rt, Addr, Decoder);
|
||||
DecodeQQQRegisterClass(Inst, Rt, Addr, Decoder);
|
||||
break;
|
||||
case ARM64::LD4i8:
|
||||
case ARM64::LD4i8_POST:
|
||||
case ARM64::LD4i16:
|
||||
case ARM64::LD4i16_POST:
|
||||
case ARM64::LD4i32:
|
||||
case ARM64::LD4i32_POST:
|
||||
case ARM64::LD4i64:
|
||||
case ARM64::LD4i64_POST:
|
||||
DecodeQQQQRegisterClass(Inst, Rt, Addr, Decoder);
|
||||
DecodeQQQQRegisterClass(Inst, Rt, Addr, Decoder);
|
||||
break;
|
||||
}
|
||||
|
||||
Inst.addOperand(MCOperand::CreateImm(index));
|
||||
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
|
||||
|
||||
switch (Inst.getOpcode()) {
|
||||
case ARM64::LD1i8_POST:
|
||||
case ARM64::LD1i16_POST:
|
||||
case ARM64::LD1i32_POST:
|
||||
case ARM64::LD1i64_POST:
|
||||
case ARM64::LD2i8_POST:
|
||||
case ARM64::LD2i16_POST:
|
||||
case ARM64::LD2i32_POST:
|
||||
case ARM64::LD2i64_POST:
|
||||
case ARM64::LD3i8_POST:
|
||||
case ARM64::LD3i16_POST:
|
||||
case ARM64::LD3i32_POST:
|
||||
case ARM64::LD3i64_POST:
|
||||
case ARM64::LD4i8_POST:
|
||||
case ARM64::LD4i16_POST:
|
||||
case ARM64::LD4i32_POST:
|
||||
case ARM64::LD4i64_POST:
|
||||
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
|
||||
break;
|
||||
}
|
||||
return Success;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user