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Simplify lowering and selection of exception ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34491 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -403,6 +403,20 @@ public:
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return StackPointerRegisterToSaveRestore;
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}
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/// getExceptionAddressRegister - If a physical register, this returns
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/// the register that receives the exception address on entry to a landing
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/// pad.
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unsigned getExceptionAddressRegister() const {
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return ExceptionPointerRegister;
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}
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/// getExceptionSelectorRegister - If a physical register, this returns
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/// the register that receives the exception typeid on entry to a landing
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/// pad.
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unsigned getExceptionSelectorRegister() const {
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return ExceptionSelectorRegister;
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}
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/// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
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/// set, the default is 200)
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unsigned getJumpBufSize() const {
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@ -604,6 +618,20 @@ protected:
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StackPointerRegisterToSaveRestore = R;
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}
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/// setExceptionPointerRegister - If set to a physical register, this sets
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/// the register that receives the exception address on entry to a landing
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/// pad.
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void setExceptionPointerRegister(unsigned R) {
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ExceptionPointerRegister = R;
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}
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/// setExceptionSelectorRegister - If set to a physical register, this sets
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/// the register that receives the exception typeid on entry to a landing
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/// pad.
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void setExceptionSelectorRegister(unsigned R) {
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ExceptionSelectorRegister = R;
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}
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/// SelectIsExpensive - Tells the code generator not to expand operations
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/// into sequences that use the select operations if possible.
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void setSelectIsExpensive() { SelectIsExpensive = true; }
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@ -956,6 +984,16 @@ private:
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/// and restore.
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unsigned StackPointerRegisterToSaveRestore;
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/// ExceptionPointerRegister - If set to a physical register, this specifies
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/// the register that receives the exception address on entry to a landing
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/// pad.
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unsigned ExceptionPointerRegister;
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/// ExceptionSelectorRegister - If set to a physical register, this specifies
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/// the register that receives the exception typeid on entry to a landing
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/// pad.
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unsigned ExceptionSelectorRegister;
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/// RegClassForVT - This indicates the default register class to use for
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/// each ValueType the target supports natively.
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TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
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@ -668,8 +668,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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break;
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case ISD::FRAMEADDR:
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case ISD::RETURNADDR:
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case ISD::EXCEPTIONADDR:
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case ISD::EHSELECTION:
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// The only option for these nodes is to custom lower them. If the target
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// does not custom lower them, then return zero.
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Tmp1 = TLI.LowerOperation(Op, DAG);
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@ -678,6 +676,32 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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else
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Result = DAG.getConstant(0, TLI.getPointerTy());
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break;
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case ISD::EHSELECTION:
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LegalizeOp(Node->getOperand(1));
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// Fall Thru
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case ISD::EXCEPTIONADDR: {
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Tmp1 = LegalizeOp(Node->getOperand(0));
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MVT::ValueType VT = Node->getValueType(0);
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switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Expand: {
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unsigned Reg = Node->getOpcode() == ISD::EXCEPTIONADDR ?
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TLI.getExceptionAddressRegister() :
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TLI.getExceptionSelectorRegister();
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Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
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}
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break;
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case TargetLowering::Custom:
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Result = TLI.LowerOperation(Op, DAG);
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if (Result.Val) break;
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// Fall Thru
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case TargetLowering::Legal:
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Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT), Tmp1).
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getValue(Op.ResNo);
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break;
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}
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}
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break;
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case ISD::AssertSext:
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case ISD::AssertZext:
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Tmp1 = LegalizeOp(Node->getOperand(0));
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