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MIR Parser: Report an error when a virtual register is redefined.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243695 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Lorenz
2015-07-30 21:54:10 +00:00
parent 8a6197a968
commit 2bc631660b
3 changed files with 34 additions and 4 deletions
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2
include/llvm/CodeGen/MIRYamlMapping.h
View File

@@ -131,7 +131,7 @@ namespace llvm {
namespace yaml { namespace yaml {
struct VirtualRegisterDefinition { struct VirtualRegisterDefinition {
unsigned ID; UnsignedValue ID;
StringValue Class; StringValue Class;
StringValue PreferredRegister; StringValue PreferredRegister;
// TODO: Serialize the target specific register hints. // TODO: Serialize the target specific register hints.

8
lib/CodeGen/MIRParser/MIRParser.cpp
View File

@@ -414,9 +414,11 @@ bool MIRParserImpl::initializeRegisterInfo(MachineFunction &MF,
Twine("use of undefined register class '") + Twine("use of undefined register class '") +
VReg.Class.Value + "'"); VReg.Class.Value + "'");
unsigned Reg = RegInfo.createVirtualRegister(RC); unsigned Reg = RegInfo.createVirtualRegister(RC);
// TODO: Report an error when the same virtual register with the same ID is if (!PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID.Value, Reg))
// redefined. .second)
PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID, Reg)); return error(VReg.ID.SourceRange.Start,
Twine("redefinition of virtual register '%") +
Twine(VReg.ID.Value) + "'");
if (!VReg.PreferredRegister.Value.empty()) { if (!VReg.PreferredRegister.Value.empty()) {
unsigned PreferredReg = 0; unsigned PreferredReg = 0;
if (parseNamedRegisterReference(PreferredReg, SM, MF, if (parseNamedRegisterReference(PreferredReg, SM, MF,

28
test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir Normal file
View File

@@ -0,0 +1,28 @@
# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @test(i32 %a) {
body:
ret i32 %a
}
...
---
name: test
isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
# CHECK: [[@LINE+1]]:11: redefinition of virtual register '%0'
- { id: 0, class: gr32 }
body:
- id: 0
name: body
liveins: [ '%edi' ]
instructions:
- '%0 = COPY %edi'
- '%eax = COPY %0'
- 'RETQ %eax'
...