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Teach the table generated emitPseudoExpansionLowering function to not emit a switch statement containing only a default statement (and no cases). Updated some of the code to use range-based for loops as well. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209521 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Aaron Ballman
parent
a4df7d473f
commit
2bd2c560ee
@ -200,70 +200,74 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
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o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
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<< "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
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<< " const MachineInstr *MI) {\n"
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<< " switch (MI->getOpcode()) {\n"
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<< " default: return false;\n";
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for (unsigned i = 0, e = Expansions.size(); i != e; ++i) {
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PseudoExpansion &Expansion = Expansions[i];
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CodeGenInstruction &Source = Expansion.Source;
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CodeGenInstruction &Dest = Expansion.Dest;
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o << " case " << Source.Namespace << "::"
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<< Source.TheDef->getName() << ": {\n"
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<< " MCInst TmpInst;\n"
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<< " MCOperand MCOp;\n"
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<< " TmpInst.setOpcode(" << Dest.Namespace << "::"
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<< Dest.TheDef->getName() << ");\n";
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<< " const MachineInstr *MI) {\n";
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// Copy the operands from the source instruction.
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// FIXME: Instruction operands with defaults values (predicates and cc_out
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// in ARM, for example shouldn't need explicit values in the
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// expansion DAG.
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unsigned MIOpNo = 0;
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for (unsigned OpNo = 0, E = Dest.Operands.size(); OpNo != E;
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++OpNo) {
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o << " // Operand: " << Dest.Operands[OpNo].Name << "\n";
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for (unsigned i = 0, e = Dest.Operands[OpNo].MINumOperands;
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i != e; ++i) {
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switch (Expansion.OperandMap[MIOpNo + i].Kind) {
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case OpData::Operand:
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o << " lowerOperand(MI->getOperand("
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<< Source.Operands[Expansion.OperandMap[MIOpNo].Data
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.Operand].MIOperandNo + i
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<< "), MCOp);\n"
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<< " TmpInst.addOperand(MCOp);\n";
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break;
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case OpData::Imm:
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o << " TmpInst.addOperand(MCOperand::CreateImm("
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<< Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
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break;
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case OpData::Reg: {
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Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
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o << " TmpInst.addOperand(MCOperand::CreateReg(";
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// "zero_reg" is special.
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if (Reg->getName() == "zero_reg")
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o << "0";
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else
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o << Reg->getValueAsString("Namespace") << "::" << Reg->getName();
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o << "));\n";
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break;
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}
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if (!Expansions.empty()) {
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o << " switch (MI->getOpcode()) {\n"
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<< " default: return false;\n";
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for (auto &Expansion : Expansions) {
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CodeGenInstruction &Source = Expansion.Source;
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CodeGenInstruction &Dest = Expansion.Dest;
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o << " case " << Source.Namespace << "::"
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<< Source.TheDef->getName() << ": {\n"
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<< " MCInst TmpInst;\n"
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<< " MCOperand MCOp;\n"
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<< " TmpInst.setOpcode(" << Dest.Namespace << "::"
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<< Dest.TheDef->getName() << ");\n";
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// Copy the operands from the source instruction.
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// FIXME: Instruction operands with defaults values (predicates and cc_out
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// in ARM, for example shouldn't need explicit values in the
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// expansion DAG.
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unsigned MIOpNo = 0;
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for (const auto &DestOperand : Dest.Operands) {
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o << " // Operand: " << DestOperand.Name << "\n";
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for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
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switch (Expansion.OperandMap[MIOpNo + i].Kind) {
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case OpData::Operand:
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o << " lowerOperand(MI->getOperand("
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<< Source.Operands[Expansion.OperandMap[MIOpNo].Data
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.Operand].MIOperandNo + i
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<< "), MCOp);\n"
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<< " TmpInst.addOperand(MCOp);\n";
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break;
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case OpData::Imm:
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o << " TmpInst.addOperand(MCOperand::CreateImm("
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<< Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
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break;
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case OpData::Reg: {
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Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
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o << " TmpInst.addOperand(MCOperand::CreateReg(";
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// "zero_reg" is special.
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if (Reg->getName() == "zero_reg")
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o << "0";
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else
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o << Reg->getValueAsString("Namespace") << "::"
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<< Reg->getName();
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o << "));\n";
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break;
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}
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}
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}
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MIOpNo += DestOperand.MINumOperands;
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}
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MIOpNo += Dest.Operands[OpNo].MINumOperands;
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if (Dest.Operands.isVariadic) {
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MIOpNo = Source.Operands.size() + 1;
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o << " // variable_ops\n";
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o << " for (unsigned i = " << MIOpNo
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<< ", e = MI->getNumOperands(); i != e; ++i)\n"
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<< " if (lowerOperand(MI->getOperand(i), MCOp))\n"
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<< " TmpInst.addOperand(MCOp);\n";
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}
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o << " EmitToStreamer(OutStreamer, TmpInst);\n"
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<< " break;\n"
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<< " }\n";
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}
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if (Dest.Operands.isVariadic) {
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MIOpNo = Source.Operands.size() + 1;
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o << " // variable_ops\n";
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o << " for (unsigned i = " << MIOpNo
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<< ", e = MI->getNumOperands(); i != e; ++i)\n"
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<< " if (lowerOperand(MI->getOperand(i), MCOp))\n"
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<< " TmpInst.addOperand(MCOp);\n";
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}
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o << " EmitToStreamer(OutStreamer, TmpInst);\n"
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<< " break;\n"
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<< " }\n";
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}
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o << " }\n return true;\n}\n\n";
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o << " }\n return true;";
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} else
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o << " return false;";
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o << "\n}\n\n";
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}
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void PseudoLoweringEmitter::run(raw_ostream &o) {
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