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Revert "Refactor UpdatePredRedefs and StepForward to avoid duplication. NFC"
This reverts commit 963cdbccf6e5578822836fd9b2ebece0ba9a60b7 (ie r236514) This is to get the bots green while i investigate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236518 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -975,18 +975,26 @@ void IfConverter::RemoveExtraEdges(BBInfo &BBI) {
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/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
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/// values defined in MI which are not live/used by MI.
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static void UpdatePredRedefs(MachineInstr *MI, LivePhysRegs &Redefs) {
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SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Clobbers;
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Redefs.stepForward(*MI, Clobbers);
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for (ConstMIBundleOperands Ops(MI); Ops.isValid(); ++Ops) {
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if (!Ops->isReg() || !Ops->isKill())
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continue;
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unsigned Reg = Ops->getReg();
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if (Reg == 0)
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continue;
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Redefs.removeReg(Reg);
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}
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for (MIBundleOperands Ops(MI); Ops.isValid(); ++Ops) {
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if (!Ops->isReg() || !Ops->isDef())
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continue;
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unsigned Reg = Ops->getReg();
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if (Reg == 0 || Redefs.contains(Reg))
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continue;
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Redefs.addReg(Reg);
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// Now add the implicit uses for each of the clobbered values.
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for (auto Reg : Clobbers) {
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const MachineOperand &Op = *Reg.second;
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// FIXME: Const cast here is nasty, but better than making StepForward
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// take a mutable instruction instead of const.
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MachineInstr *OpMI = const_cast<MachineInstr*>(Op.getParent());
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MachineInstrBuilder MIB(*OpMI->getParent()->getParent(), OpMI);
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assert(Op.isReg() && "Register operand required");
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MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
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MachineOperand &Op = *Ops;
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MachineInstr *MI = Op.getParent();
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MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
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MIB.addReg(Reg, RegState::Implicit | RegState::Undef);
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}
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}
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@ -1366,8 +1374,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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for (MachineBasicBlock::const_iterator I = BBI1->BB->begin(), E = DI1; I != E;
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++I) {
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SmallVector<std::pair<unsigned, const MachineOperand*>, 4> IgnoredClobbers;
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Redefs.stepForward(*I, IgnoredClobbers);
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Redefs.stepForward(*I);
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}
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BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1);
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BBI2->BB->erase(BBI2->BB->begin(), DI2);
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