mirror of
https://github.com/c64scene-ar/llvm-6502.git
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All "integer" logical ops (pand, por, pxor) are now promoted to v2i64.
Clean up and fix various logical ops issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27633 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
cc9876124e
commit
2c3ae37213
@ -794,3 +794,7 @@ http://llvm.org/bugs/show_bug.cgi?id=729
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X86RegisterInfo::copyRegToReg() returns X86::MOVAPSrr for VR128. Is it possible
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to choose between movaps, movapd, and movdqa based on types of source and
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destination?
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How about andps, andpd, and pand? Do we really care about the type of the packed
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elements? If not, why not always use the "ps" variants which are likely to be
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shorter.
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@ -275,6 +275,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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if (Subtarget->hasSSE1()) {
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addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
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setOperationAction(ISD::AND, MVT::v4f32, Legal);
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setOperationAction(ISD::OR, MVT::v4f32, Legal);
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setOperationAction(ISD::XOR, MVT::v4f32, Legal);
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setOperationAction(ISD::ADD, MVT::v4f32, Legal);
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setOperationAction(ISD::SUB, MVT::v4f32, Legal);
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setOperationAction(ISD::MUL, MVT::v4f32, Legal);
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@ -301,36 +304,43 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SUB, MVT::v8i16, Legal);
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setOperationAction(ISD::SUB, MVT::v4i32, Legal);
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setOperationAction(ISD::MUL, MVT::v2f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
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// Promote v16i8, v8i16, v4i32 selects to v2i64. Custom lower v2i64, v2f64,
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// and v4f32 selects.
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for (unsigned VT = (unsigned)MVT::v16i8;
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VT != (unsigned)MVT::v2i64; VT++) {
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setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
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AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
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// Custom lower build_vector, vector_shuffle, and extract_vector_elt.
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for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
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setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
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}
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
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// Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
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for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
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setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
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AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
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setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
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AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
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setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
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AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
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setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
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AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
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setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
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AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
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}
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// Custom lower v2i64 and v2f64 selects.
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setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
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setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
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setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
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}
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// We want to custom lower some of our intrinsics.
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@ -2827,6 +2837,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return SDOperand();
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MVT::ValueType VT = Op.getValueType();
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// TODO: handle v16i8.
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if (MVT::getSizeInBits(VT) == 16) {
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// Transform it so it match pextrw which produces a 32-bit result.
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MVT::ValueType EVT = (MVT::ValueType)(VT+1);
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@ -1019,9 +1019,7 @@ let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(and (bc_v4i32 (v4f32 VR128:$src1)),
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(bc_v4i32 (v4f32 VR128:$src2))))]>;
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[(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
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def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"andpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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@ -1029,9 +1027,7 @@ def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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(bc_v2i64 (v2f64 VR128:$src2))))]>;
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def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"orps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(or (bc_v4i32 (v4f32 VR128:$src1)),
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(bc_v4i32 (v4f32 VR128:$src2))))]>;
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[(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
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def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"orpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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@ -1039,9 +1035,7 @@ def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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(bc_v2i64 (v2f64 VR128:$src2))))]>;
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def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"xorps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(xor (bc_v4i32 (v4f32 VR128:$src1)),
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(bc_v4i32 (v4f32 VR128:$src2))))]>;
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[(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
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def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"xorpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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@ -1050,9 +1044,8 @@ def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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}
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def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(and (bc_v4i32 (v4f32 VR128:$src1)),
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(bc_v4i32 (loadv4f32 addr:$src2))))]>;
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[(set VR128:$dst, (and VR128:$src1,
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(bc_v2i64 (loadv4f32 addr:$src2))))]>;
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def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"andpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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@ -1060,9 +1053,8 @@ def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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(bc_v2i64 (loadv2f64 addr:$src2))))]>;
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def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"orps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(or (bc_v4i32 (v4f32 VR128:$src1)),
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(bc_v4i32 (loadv4f32 addr:$src2))))]>;
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[(set VR128:$dst, (or VR128:$src1,
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(bc_v2i64 (loadv4f32 addr:$src2))))]>;
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def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"orpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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@ -1070,9 +1062,8 @@ def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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(bc_v2i64 (loadv2f64 addr:$src2))))]>;
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def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"xorps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(xor (bc_v4i32 (v4f32 VR128:$src1)),
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(bc_v4i32 (loadv4f32 addr:$src2))))]>;
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[(set VR128:$dst, (xor VR128:$src1,
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(bc_v2i64 (loadv4f32 addr:$src2))))]>;
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def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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"xorpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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@ -1080,14 +1071,14 @@ def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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(bc_v2i64 (loadv2f64 addr:$src2))))]>;
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def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"andnps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(and (vnot (bc_v4i32 (v4f32 VR128:$src1))),
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(bc_v4i32 (v4f32 VR128:$src2))))]>;
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[(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
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(bc_v2i64 (v4i32 immAllOnesV))),
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VR128:$src2)))]>;
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def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
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"andnps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(and (vnot (bc_v4i32 (v4f32 VR128:$src1))),
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(bc_v4i32 (loadv4f32 addr:$src2))))]>;
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[(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
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(bc_v2i64 (v4i32 immAllOnesV))),
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(bc_v2i64 (loadv4f32 addr:$src2)))))]>;
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def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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"andnpd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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@ -1922,110 +1913,29 @@ def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
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// 128-bit logical shifts
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def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
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(v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
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(v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
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Requires<[HasSSE2]>;
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def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
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(v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
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(v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
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Requires<[HasSSE2]>;
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// Logical ops
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def : Pat<(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
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(ANDPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(and (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
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(ANDPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(or (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
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(ORPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(or (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
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(ORPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(xor (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
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(XORPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(xor (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
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(XORPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(and (vnot (bc_v4i32 (v4f32 VR128:$src1))), (loadv4i32 addr:$src2)),
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(ANDNPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(and (vnot (bc_v2i64 (v2f64 VR128:$src1))), (loadv2i64 addr:$src2)),
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(ANDNPDrm VR128:$src1, addr:$src2)>;
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// Some special case pandn patterns.
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def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
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VR128:$src2)),
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(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
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VR128:$src2)),
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(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
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VR128:$src2)),
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(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
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def : Pat<(bc_v4f32 (v4i32 (and VR128:$src1, VR128:$src2))),
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(ANDPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(bc_v4f32 (v4i32 (or VR128:$src1, VR128:$src2))),
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(ORPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(bc_v4f32 (v4i32 (xor VR128:$src1, VR128:$src2))),
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(XORPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(bc_v4f32 (v4i32 (and (vnot VR128:$src1), VR128:$src2))),
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(ANDNPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(bc_v4f32 (v4i32 (and VR128:$src1, (load addr:$src2)))),
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(ANDPSrm (v4i32 VR128:$src1), addr:$src2)>;
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def : Pat<(bc_v4f32 (v4i32 (or VR128:$src1, (load addr:$src2)))),
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(ORPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(bc_v4f32 (v4i32 (xor VR128:$src1, (load addr:$src2)))),
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(XORPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(bc_v4f32 (v4i32 (and (vnot VR128:$src1), (load addr:$src2)))),
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(ANDNPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(bc_v2f64 (v2i64 (and VR128:$src1, VR128:$src2))),
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(ANDPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(bc_v2f64 (v2i64 (or VR128:$src1, VR128:$src2))),
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(ORPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(bc_v2f64 (v2i64 (xor VR128:$src1, VR128:$src2))),
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(XORPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(bc_v2f64 (v2i64 (and (vnot VR128:$src1), VR128:$src2))),
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(ANDNPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(bc_v2f64 (v2i64 (and VR128:$src1, (load addr:$src2)))),
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(ANDPSrm (v2i64 VR128:$src1), addr:$src2)>;
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def : Pat<(bc_v2f64 (v2i64 (or VR128:$src1, (load addr:$src2)))),
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(ORPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(bc_v2f64 (v2i64 (xor VR128:$src1, (load addr:$src2)))),
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(XORPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(bc_v2f64 (v2i64 (and (vnot VR128:$src1), (load addr:$src2)))),
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(ANDNPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (and VR128:$src1, VR128:$src2)),
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(PANDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (and VR128:$src1, VR128:$src2)),
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(PANDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v16i8 (and VR128:$src1, VR128:$src2)),
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(PANDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (or VR128:$src1, VR128:$src2)),
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(PORrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (or VR128:$src1, VR128:$src2)),
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(PORrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v16i8 (or VR128:$src1, VR128:$src2)),
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(PORrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v4i32 (xor VR128:$src1, VR128:$src2)),
|
||||
(PXORrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v8i16 (xor VR128:$src1, VR128:$src2)),
|
||||
(PXORrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v16i8 (xor VR128:$src1, VR128:$src2)),
|
||||
(PXORrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v4i32 (and (vnot VR128:$src1), VR128:$src2)),
|
||||
(PANDNrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v8i16 (and (vnot VR128:$src1), VR128:$src2)),
|
||||
(PANDNrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v16i8 (and (vnot VR128:$src1), VR128:$src2)),
|
||||
(PANDNrr VR128:$src1, VR128:$src2)>;
|
||||
|
||||
def : Pat<(v4i32 (and VR128:$src1, (load addr:$src2))),
|
||||
(PANDrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i16 (and VR128:$src1, (load addr:$src2))),
|
||||
(PANDrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v16i8 (and VR128:$src1, (load addr:$src2))),
|
||||
(PANDrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i32 (or VR128:$src1, (load addr:$src2))),
|
||||
(PORrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i16 (or VR128:$src1, (load addr:$src2))),
|
||||
(PORrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v16i8 (or VR128:$src1, (load addr:$src2))),
|
||||
(PORrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i32 (xor VR128:$src1, (load addr:$src2))),
|
||||
(PXORrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i16 (xor VR128:$src1, (load addr:$src2))),
|
||||
(PXORrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v16i8 (xor VR128:$src1, (load addr:$src2))),
|
||||
(PXORrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i32 (and (vnot VR128:$src1), (load addr:$src2))),
|
||||
(PANDNrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i16 (and (vnot VR128:$src1), (load addr:$src2))),
|
||||
(PANDNrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v16i8 (and (vnot VR128:$src1), (load addr:$src2))),
|
||||
(PANDNrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
|
||||
(load addr:$src2))),
|
||||
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
|
||||
(load addr:$src2))),
|
||||
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
|
||||
(load addr:$src2))),
|
||||
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user