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Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156195 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sebastian Pop
2012-05-04 19:53:56 +00:00
parent 3d142e58ef
commit 2c7e5c714c
2 changed files with 15 additions and 4 deletions
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1
lib/Target/ARM/Thumb2SizeReduction.cpp
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@ -67,6 +67,7 @@ namespace {
{ ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0 }, { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0 },
//FIXME: Disable CMN, as CCodes are backwards from compare expectations //FIXME: Disable CMN, as CCodes are backwards from compare expectations
//{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0 }, //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0 },
{ ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0 },
{ ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0 }, { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0 },
{ ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1 }, { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1 },
{ ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0 }, { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0 },

18
test/CodeGen/Thumb2/thumb2-cmn.ll
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@ -9,7 +9,7 @@ define i1 @f1(i32 %a, i32 %b) {
ret i1 %tmp ret i1 %tmp
} }
; CHECK: f1: ; CHECK: f1:
; CHECK: cmn.w r0, r1 ; CHECK: cmn r0, r1
define i1 @f2(i32 %a, i32 %b) { define i1 @f2(i32 %a, i32 %b) {
%nb = sub i32 0, %b %nb = sub i32 0, %b
@ -17,7 +17,7 @@ define i1 @f2(i32 %a, i32 %b) {
ret i1 %tmp ret i1 %tmp
} }
; CHECK: f2: ; CHECK: f2:
; CHECK: cmn.w r0, r1 ; CHECK: cmn r0, r1
define i1 @f3(i32 %a, i32 %b) { define i1 @f3(i32 %a, i32 %b) {
%nb = sub i32 0, %b %nb = sub i32 0, %b
@ -25,7 +25,7 @@ define i1 @f3(i32 %a, i32 %b) {
ret i1 %tmp ret i1 %tmp
} }
; CHECK: f3: ; CHECK: f3:
; CHECK: cmn.w r0, r1 ; CHECK: cmn r0, r1
define i1 @f4(i32 %a, i32 %b) { define i1 @f4(i32 %a, i32 %b) {
%nb = sub i32 0, %b %nb = sub i32 0, %b
@ -33,7 +33,7 @@ define i1 @f4(i32 %a, i32 %b) {
ret i1 %tmp ret i1 %tmp
} }
; CHECK: f4: ; CHECK: f4:
; CHECK: cmn.w r0, r1 ; CHECK: cmn r0, r1
define i1 @f5(i32 %a, i32 %b) { define i1 @f5(i32 %a, i32 %b) {
%tmp = shl i32 %b, 5 %tmp = shl i32 %b, 5
@ -73,3 +73,13 @@ define i1 @f8(i32 %a, i32 %b) {
; CHECK: f8: ; CHECK: f8:
; CHECK: cmn.w r0, r0, ror #8 ; CHECK: cmn.w r0, r0, ror #8
define void @f9(i32 %a, i32 %b) nounwind optsize {
tail call void asm sideeffect "cmn.w r0, r1", ""() nounwind, !srcloc !0
ret void
}
!0 = metadata !{i32 81}
; CHECK: f9:
; CHECK: cmn.w r0, r1