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Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1474,6 +1474,12 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
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bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
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// Sanity check the registers, which should not be 15.
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if (decodeRd(insn) == 15 || decodeRm(insn) == 15)
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return false;
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if (ThreeReg && decodeRn(insn) == 15)
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return false;
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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decodeRd(insn))));
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decodeRd(insn))));
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++OpIdx;
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++OpIdx;
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@ -1498,7 +1504,7 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
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ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
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if (Opcode == ARM::PKHBT)
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if (Opcode == ARM::PKHBT)
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Opc = ARM_AM::lsl;
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Opc = ARM_AM::lsl;
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else if (Opcode == ARM::PKHBT)
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else if (Opcode == ARM::PKHTB)
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Opc = ARM_AM::asr;
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Opc = ARM_AM::asr;
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getImmShiftSE(Opc, ShiftAmt);
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getImmShiftSE(Opc, ShiftAmt);
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MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));
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MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));
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@ -76,9 +76,12 @@
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# CHECK: pkhbt r8, r9, r10, lsl #4
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# CHECK: pkhbt r8, r9, r10, lsl #4
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0x1a 0x82 0x89 0xe6
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0x1a 0x82 0x89 0xe6
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# CHECK-NOT: pkhbtls pc, r11, r11, lsl #0
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# CHECK-NOT: pkhbtls r10, r11, r11, lsl #0
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# CHECK: pkhbtls pc, r11, r11
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# CHECK: pkhbtls r10, r11, r11
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0x1b 0xf0 0x8b 0x96
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0x1b 0xa0 0x8b 0x96
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# CHECK: pkhtbmi lr, r1, r6, asr #21
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0xd6 0xea 0x81 0x46
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# CHECK: pop {r0, r2, r4, r6, r8, r10}
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# CHECK: pop {r0, r2, r4, r6, r8, r10}
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0x55 0x05 0xbd 0xe8
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0x55 0x05 0xbd 0xe8
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