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Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register

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encodings for DisassembleArithMiscFrm().

rdar://problem/9238659


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-05 23:28:00 +00:00
parent e4dc1966ba
commit 2c868d1eef
2 changed files with 13 additions and 4 deletions
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8
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -1474,6 +1474,12 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
// Sanity check the registers, which should not be 15.
if (decodeRd(insn) == 15 || decodeRm(insn) == 15)
return false;
if (ThreeReg && decodeRn(insn) == 15)
return false;
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRd(insn))));
++OpIdx;
@ -1498,7 +1504,7 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
if (Opcode == ARM::PKHBT)
Opc = ARM_AM::lsl;
else if (Opcode == ARM::PKHBT)
else if (Opcode == ARM::PKHTB)
Opc = ARM_AM::asr;
getImmShiftSE(Opc, ShiftAmt);
MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));

9
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -76,9 +76,12 @@
# CHECK: pkhbt r8, r9, r10, lsl #4
0x1a 0x82 0x89 0xe6
# CHECK-NOT: pkhbtls pc, r11, r11, lsl #0
# CHECK: pkhbtls pc, r11, r11
0x1b 0xf0 0x8b 0x96
# CHECK-NOT: pkhbtls r10, r11, r11, lsl #0
# CHECK: pkhbtls r10, r11, r11
0x1b 0xa0 0x8b 0x96
# CHECK: pkhtbmi lr, r1, r6, asr #21
0xd6 0xea 0x81 0x46
# CHECK: pop {r0, r2, r4, r6, r8, r10}
0x55 0x05 0xbd 0xe8