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Revert "[mips] Add names and tests for the hardware registers"

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This reverts commit r221299.

The tests

    LLVM :: MC/Disassembler/Mips/mips32.txt
    LLVM :: MC/Disassembler/Mips/mips32_le.txt

were failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221307 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2014-11-04 22:15:05 +00:00
parent f49ead7098
commit 2ca0328c3b
10 changed files with 8 additions and 266 deletions
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31
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@@ -222,8 +222,6 @@ class MipsAsmParser : public MCTargetAsmParser {
int matchCPURegisterName(StringRef Symbol);
int matchHWRegsRegisterName(StringRef Symbol);
int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
int matchFPURegisterName(StringRef Name);
@@ -861,14 +859,6 @@ public:
return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
}
/// Create a register that is definitely a HWReg.
/// This is typically only used for named registers such as $hwr_cpunum.
static std::unique_ptr<MipsOperand>
createHWRegsReg(unsigned Index, const MCRegisterInfo *RegInfo,
SMLoc S, SMLoc E, MipsAsmParser &Parser) {
return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser);
}
/// Create a register that is definitely an FCC.
/// This is typically only used for named registers such as $fcc0.
static std::unique_ptr<MipsOperand>
@@ -1805,20 +1795,6 @@ int MipsAsmParser::matchCPURegisterName(StringRef Name) {
return CC;
}
int MipsAsmParser::matchHWRegsRegisterName(StringRef Name) {
int CC;
CC = StringSwitch<unsigned>(Name)
.Case("hwr_cpunum", 0)
.Case("hwr_synci_step", 1)
.Case("hwr_cc", 2)
.Case("hwr_ccres", 3)
.Case("hwr_ulr", 29)
.Default(-1);
return CC;
}
int MipsAsmParser::matchFPURegisterName(StringRef Name) {
if (Name[0] == 'f') {
@@ -2302,13 +2278,6 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
return MatchOperand_Success;
}
Index = matchHWRegsRegisterName(Identifier);
if (Index != -1) {
Operands.push_back(MipsOperand::createHWRegsReg(
Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
return MatchOperand_Success;
}
Index = matchFPURegisterName(Identifier);
if (Index != -1) {
Operands.push_back(MipsOperand::createFGRReg(

10
lib/Target/Mips/MipsRegisterInfo.td
View File

@@ -212,14 +212,8 @@ let Namespace = "Mips" in {
// PC register
def PC : Register<"pc">;
// Hardware registers
def HWR0 : MipsReg<0, "hwr_cpunum">;
def HWR1 : MipsReg<1, "hwr_synci_step">;
def HWR2 : MipsReg<2, "hwr_cc">;
def HWR3 : MipsReg<3, "hwr_ccres">;
def HWR29 : MipsReg<29, "hwr_ulr">;
foreach I = {4-28,30-31} in
// Hardware register $29
foreach I = 0-31 in
def HWR#I : MipsReg<#I, ""#I>;
// Accum registers