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Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-08-08 19:49:37 +00:00
parent 08de97a5b0
commit 2cb1dfa446
2 changed files with 35 additions and 5 deletions
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11
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -977,7 +977,8 @@ multiclass T2I_st<bits<2> opcod, string opc,
class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
: T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
opc, ".w\t$Rd, $Rm$rot",
[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsThumb2]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod;
@ -3407,9 +3408,9 @@ def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
// SXT/UXT with no rotate
let AddedComplexity = 16 in {
def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
Requires<[IsThumb2]>;
def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
Requires<[IsThumb2]>;
def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
@ -3421,9 +3422,9 @@ def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
}
def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
Requires<[IsThumb2]>;
def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;
Requires<[IsThumb2]>;
def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
(t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
Requires<[HasT2ExtractPack, IsThumb2]>;

29
test/CodeGen/Thumb2/thumb2-sxt-uxt.ll Normal file
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@ -0,0 +1,29 @@
; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s
define i32 @test1(i16 zeroext %z) nounwind {
; CHECK: test1:
; CHECK: sxth
%r = sext i16 %z to i32
ret i32 %r
}
define i32 @test2(i8 zeroext %z) nounwind {
; CHECK: test2:
; CHECK: sxtb
%r = sext i8 %z to i32
ret i32 %r
}
define i32 @test3(i16 signext %z) nounwind {
; CHECK: test3:
; CHECK: uxth
%r = zext i16 %z to i32
ret i32 %r
}
define i32 @test4(i8 signext %z) nounwind {
; CHECK: test4:
; CHECK: uxtb
%r = zext i8 %z to i32
ret i32 %r
}