mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-04 02:24:29 +00:00
VirtRegRewriter spring cleaning. No functional change.
Move methods out of line and M-x whitespace-cleanup. Promote common method arguments to member variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98207 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
@ -1037,33 +1037,80 @@ void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg,
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}
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namespace {
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struct RefSorter {
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bool operator()(const std::pair<MachineInstr*, int> &A,
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const std::pair<MachineInstr*, int> &B) {
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return A.second < B.second;
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}
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};
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}
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// ***************************** //
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// Local Spiller Implementation //
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// ***************************** //
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namespace {
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class LocalRewriter : public VirtRegRewriter {
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MachineRegisterInfo *RegInfo;
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MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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VirtRegMap *VRM;
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BitVector AllocatableRegs;
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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MachineBasicBlock *MBB; // Basic block currently being processed.
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public:
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bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
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LiveIntervals* LIs);
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private:
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bool OptimizeByUnfold2(unsigned VirtReg, int SS,
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MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps);
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bool OptimizeByUnfold(MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps);
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bool CommuteToFoldReload(MachineBasicBlock::iterator &MII,
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unsigned VirtReg, unsigned SrcReg, int SS,
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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const TargetRegisterInfo *TRI);
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void SpillRegToStackSlot(MachineBasicBlock::iterator &MII,
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int Idx, unsigned PhysReg, int StackSlot,
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const TargetRegisterClass *RC,
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bool isAvailable, MachineInstr *&LastStore,
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AvailableSpills &Spills,
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SmallSet<MachineInstr*, 4> &ReMatDefs,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps);
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void TransferDeadness(unsigned CurDist,
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unsigned Reg, BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps);
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void RewriteMBB(LiveIntervals *LIs,
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AvailableSpills &Spills, BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps);
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};
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}
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bool LocalRewriter::runOnMachineFunction(MachineFunction &MF, VirtRegMap &vrm,
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LiveIntervals* LIs) {
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RegInfo = &MF.getRegInfo();
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MRI = &MF.getRegInfo();
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TRI = MF.getTarget().getRegisterInfo();
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TII = MF.getTarget().getInstrInfo();
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VRM = &vrm;
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AllocatableRegs = TRI->getAllocatableSet(MF);
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DEBUG(dbgs() << "\n**** Local spiller rewriting function '"
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<< MF.getFunction()->getName() << "':\n");
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@ -1092,9 +1139,9 @@ public:
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SmallPtrSet<MachineBasicBlock*,16> >
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DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
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DFI != E; ++DFI) {
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MachineBasicBlock *MBB = *DFI;
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MBB = *DFI;
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if (!EarlyVisited.count(MBB))
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RewriteMBB(*MBB, VRM, LIs, Spills, RegKills, KillOps);
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RewriteMBB(LIs, Spills, RegKills, KillOps);
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// If this MBB is the only predecessor of a successor. Keep the
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// availability information and visit it next.
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@ -1110,7 +1157,7 @@ public:
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MBB = SinglePredSuccs[0];
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if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) {
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Spills.AddAvailableRegsToLiveIn(*MBB, RegKills, KillOps);
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RewriteMBB(*MBB, VRM, LIs, Spills, RegKills, KillOps);
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RewriteMBB(LIs, Spills, RegKills, KillOps);
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}
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}
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} while (MBB);
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@ -1124,10 +1171,10 @@ public:
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// Mark unused spill slots.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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int SS = VRM.getLowSpillSlot();
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int SS = VRM->getLowSpillSlot();
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if (SS != VirtRegMap::NO_STACK_SLOT)
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for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS)
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if (!VRM.isSpillSlotUsed(SS)) {
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for (int e = VRM->getHighSpillSlot(); SS <= e; ++SS)
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if (!VRM->isSpillSlotUsed(SS)) {
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MFI->RemoveStackObject(SS);
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++NumDSS;
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}
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@ -1135,8 +1182,6 @@ public:
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return true;
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}
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private:
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/// OptimizeByUnfold2 - Unfold a series of load / store folding instructions if
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/// a scratch register is available.
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/// xorq %r12<kill>, %r13
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@ -1148,17 +1193,16 @@ private:
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/// addq %rax, %r12
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/// addq %r13, %r12
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/// movq %r12, -184(%rbp)
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bool OptimizeByUnfold2(unsigned VirtReg, int SS,
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MachineBasicBlock &MBB,
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bool LocalRewriter::
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OptimizeByUnfold2(unsigned VirtReg, int SS,
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MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM) {
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std::vector<MachineOperand*> &KillOps) {
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MachineBasicBlock::iterator NextMII = llvm::next(MII);
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if (NextMII == MBB.end())
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if (NextMII == MBB->end())
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return false;
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if (TII->getOpcodeAfterMemoryUnfold(MII->getOpcode(), true, true) == 0)
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@ -1166,28 +1210,28 @@ private:
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// Now let's see if the last couple of instructions happens to have freed up
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// a register.
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const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
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unsigned PhysReg = FindFreeRegister(MII, MBB, RC, TRI, AllocatableRegs);
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const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
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unsigned PhysReg = FindFreeRegister(MII, *MBB, RC, TRI, AllocatableRegs);
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if (!PhysReg)
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return false;
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB->getParent();
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TRI = MF.getTarget().getRegisterInfo();
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MachineInstr &MI = *MII;
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if (!FoldsStackSlotModRef(MI, SS, PhysReg, TII, TRI, VRM))
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if (!FoldsStackSlotModRef(MI, SS, PhysReg, TII, TRI, *VRM))
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return false;
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// If the next instruction also folds the same SS modref and can be unfoled,
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// then it's worthwhile to issue a load from SS into the free register and
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// then unfold these instructions.
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if (!FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM))
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if (!FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, *VRM))
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return false;
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// Back-schedule reloads and remats.
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ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF);
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ComputeReloadLoc(MII, MBB->begin(), PhysReg, TRI, false, SS, TII, MF);
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// Load from SS to the spare physical register.
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TII->loadRegFromStackSlot(MBB, MII, PhysReg, SS, RC);
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TII->loadRegFromStackSlot(*MBB, MII, PhysReg, SS, RC);
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// This invalidates Phys.
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Spills.ClobberPhysReg(PhysReg);
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// Remember it's available.
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@ -1200,11 +1244,11 @@ private:
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llvm_unreachable("Unable unfold the load / store folding instruction!");
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assert(NewMIs.size() == 1);
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AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI);
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VRM.transferRestorePts(&MI, NewMIs[0]);
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MII = MBB.insert(MII, NewMIs[0]);
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VRM->transferRestorePts(&MI, NewMIs[0]);
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MII = MBB->insert(MII, NewMIs[0]);
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InvalidateKills(MI, TRI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(&MI);
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MBB.erase(&MI);
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VRM->RemoveMachineInstrFromMaps(&MI);
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MBB->erase(&MI);
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++NumModRefUnfold;
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// Unfold next instructions that fold the same SS.
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@ -1216,21 +1260,21 @@ private:
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llvm_unreachable("Unable unfold the load / store folding instruction!");
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assert(NewMIs.size() == 1);
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AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI);
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VRM.transferRestorePts(&NextMI, NewMIs[0]);
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MBB.insert(NextMII, NewMIs[0]);
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VRM->transferRestorePts(&NextMI, NewMIs[0]);
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MBB->insert(NextMII, NewMIs[0]);
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InvalidateKills(NextMI, TRI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(&NextMI);
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MBB.erase(&NextMI);
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VRM->RemoveMachineInstrFromMaps(&NextMI);
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MBB->erase(&NextMI);
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++NumModRefUnfold;
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if (NextMII == MBB.end())
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if (NextMII == MBB->end())
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break;
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} while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM));
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} while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, *VRM));
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// Store the value back into SS.
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TII->storeRegToStackSlot(MBB, NextMII, PhysReg, true, SS, RC);
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TII->storeRegToStackSlot(*MBB, NextMII, PhysReg, true, SS, RC);
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MachineInstr *StoreMI = prior(NextMII);
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VRM.addSpillSlotUse(SS, StoreMI);
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VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
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VRM->addSpillSlotUse(SS, StoreMI);
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VRM->virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
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return true;
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}
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@ -1247,21 +1291,20 @@ private:
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/// mov %eax, -32(%ebp)
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/// This enables unfolding optimization for a subsequent instruction which will
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/// also eliminate the newly introduced store instruction.
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bool OptimizeByUnfold(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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bool LocalRewriter::
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OptimizeByUnfold(MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM) {
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MachineFunction &MF = *MBB.getParent();
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std::vector<MachineOperand*> &KillOps) {
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MachineFunction &MF = *MBB->getParent();
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MachineInstr &MI = *MII;
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unsigned UnfoldedOpc = 0;
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unsigned UnfoldPR = 0;
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unsigned UnfoldVR = 0;
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int FoldedSS = VirtRegMap::NO_STACK_SLOT;
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VirtRegMap::MI2VirtMapTy::const_iterator I, End;
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for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
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for (tie(I, End) = VRM->getFoldedVirts(&MI); I != End; ) {
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// Only transform a MI that folds a single register.
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if (UnfoldedOpc)
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return false;
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@ -1270,11 +1313,11 @@ private:
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// MI2VirtMap be can updated which invalidate the iterator.
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// Increment the iterator first.
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++I;
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if (VRM.isAssignedReg(UnfoldVR))
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if (VRM->isAssignedReg(UnfoldVR))
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continue;
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// If this reference is not a use, any previous store is now dead.
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// Otherwise, the store to this stack slot is not dead anymore.
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FoldedSS = VRM.getStackSlot(UnfoldVR);
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FoldedSS = VRM->getStackSlot(UnfoldVR);
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MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
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if (DeadStore && (MR & VirtRegMap::isModRef)) {
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unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
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@ -1291,8 +1334,8 @@ private:
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return false;
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// Look for other unfolding opportunities.
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return OptimizeByUnfold2(UnfoldVR, FoldedSS, MBB, MII,
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MaybeDeadStores, Spills, RegKills, KillOps, VRM);
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return OptimizeByUnfold2(UnfoldVR, FoldedSS, MII, MaybeDeadStores, Spills,
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RegKills, KillOps);
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}
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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@ -1302,21 +1345,21 @@ private:
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unsigned VirtReg = MO.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
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continue;
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if (VRM.isAssignedReg(VirtReg)) {
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unsigned PhysReg = VRM.getPhys(VirtReg);
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if (VRM->isAssignedReg(VirtReg)) {
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unsigned PhysReg = VRM->getPhys(VirtReg);
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if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
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return false;
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} else if (VRM.isReMaterialized(VirtReg))
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} else if (VRM->isReMaterialized(VirtReg))
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continue;
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int SS = VRM.getStackSlot(VirtReg);
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int SS = VRM->getStackSlot(VirtReg);
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unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
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if (PhysReg) {
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if (TRI->regsOverlap(PhysReg, UnfoldPR))
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return false;
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continue;
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}
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if (VRM.hasPhys(VirtReg)) {
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PhysReg = VRM.getPhys(VirtReg);
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if (VRM->hasPhys(VirtReg)) {
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PhysReg = VRM->getPhys(VirtReg);
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if (!TRI->regsOverlap(PhysReg, UnfoldPR))
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continue;
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}
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@ -1337,14 +1380,14 @@ private:
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Ops.push_back(Idx);
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MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
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if (FoldedMI) {
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VRM.addSpillSlotUse(SS, FoldedMI);
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if (!VRM.hasPhys(UnfoldVR))
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VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
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VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
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MII = MBB.insert(MII, FoldedMI);
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VRM->addSpillSlotUse(SS, FoldedMI);
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if (!VRM->hasPhys(UnfoldVR))
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VRM->assignVirt2Phys(UnfoldVR, UnfoldPR);
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VRM->virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
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MII = MBB->insert(MII, FoldedMI);
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InvalidateKills(MI, TRI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(&MI);
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MBB.erase(&MI);
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VRM->RemoveMachineInstrFromMaps(&MI);
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MBB->erase(&MI);
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MF.DeleteMachineInstr(NewMI);
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return true;
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}
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@ -1390,24 +1433,23 @@ private:
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/// If op is commutable and r2 is killed, then we can xform these to
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/// r2 = op r2, fi#1
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/// store r2, fi#1
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bool CommuteToFoldReload(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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bool LocalRewriter::
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CommuteToFoldReload(MachineBasicBlock::iterator &MII,
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unsigned VirtReg, unsigned SrcReg, int SS,
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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const TargetRegisterInfo *TRI,
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VirtRegMap &VRM) {
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if (MII == MBB.begin() || !MII->killsRegister(SrcReg))
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const TargetRegisterInfo *TRI) {
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if (MII == MBB->begin() || !MII->killsRegister(SrcReg))
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return false;
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MachineFunction &MF = *MBB.getParent();
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MachineFunction &MF = *MBB->getParent();
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MachineInstr &MI = *MII;
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MachineBasicBlock::iterator DefMII = prior(MII);
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MachineInstr *DefMI = DefMII;
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const TargetInstrDesc &TID = DefMI->getDesc();
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unsigned NewDstIdx;
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if (DefMII != MBB.begin() &&
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if (DefMII != MBB->begin() &&
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TID.isCommutable() &&
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CommuteChangesDestination(DefMI, TID, SrcReg, TII, NewDstIdx)) {
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MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
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@ -1440,27 +1482,27 @@ private:
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if (!FoldedMI)
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return false;
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VRM.addSpillSlotUse(SS, FoldedMI);
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VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
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VRM->addSpillSlotUse(SS, FoldedMI);
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VRM->virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
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// Insert new def MI and spill MI.
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const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
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TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC);
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const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
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TII->storeRegToStackSlot(*MBB, &MI, NewReg, true, SS, RC);
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MII = prior(MII);
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MachineInstr *StoreMI = MII;
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VRM.addSpillSlotUse(SS, StoreMI);
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VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
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MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack.
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VRM->addSpillSlotUse(SS, StoreMI);
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VRM->virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
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MII = MBB->insert(MII, FoldedMI); // Update MII to backtrack.
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// Delete all 3 old instructions.
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InvalidateKills(*ReloadMI, TRI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(ReloadMI);
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MBB.erase(ReloadMI);
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VRM->RemoveMachineInstrFromMaps(ReloadMI);
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MBB->erase(ReloadMI);
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InvalidateKills(*DefMI, TRI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(DefMI);
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MBB.erase(DefMI);
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VRM->RemoveMachineInstrFromMaps(DefMI);
|
||||
MBB->erase(DefMI);
|
||||
InvalidateKills(MI, TRI, RegKills, KillOps);
|
||||
VRM.RemoveMachineInstrFromMaps(&MI);
|
||||
MBB.erase(&MI);
|
||||
VRM->RemoveMachineInstrFromMaps(&MI);
|
||||
MBB->erase(&MI);
|
||||
|
||||
// If NewReg was previously holding value of some SS, it's now clobbered.
|
||||
// This has to be done now because it's a physical register. When this
|
||||
@ -1476,21 +1518,20 @@ private:
|
||||
|
||||
/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
|
||||
/// the last store to the same slot is now dead. If so, remove the last store.
|
||||
void SpillRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator &MII,
|
||||
void LocalRewriter::
|
||||
SpillRegToStackSlot(MachineBasicBlock::iterator &MII,
|
||||
int Idx, unsigned PhysReg, int StackSlot,
|
||||
const TargetRegisterClass *RC,
|
||||
bool isAvailable, MachineInstr *&LastStore,
|
||||
AvailableSpills &Spills,
|
||||
SmallSet<MachineInstr*, 4> &ReMatDefs,
|
||||
BitVector &RegKills,
|
||||
std::vector<MachineOperand*> &KillOps,
|
||||
VirtRegMap &VRM) {
|
||||
std::vector<MachineOperand*> &KillOps) {
|
||||
|
||||
MachineBasicBlock::iterator oldNextMII = llvm::next(MII);
|
||||
TII->storeRegToStackSlot(MBB, llvm::next(MII), PhysReg, true, StackSlot, RC);
|
||||
TII->storeRegToStackSlot(*MBB, llvm::next(MII), PhysReg, true, StackSlot, RC);
|
||||
MachineInstr *StoreMI = prior(oldNextMII);
|
||||
VRM.addSpillSlotUse(StackSlot, StoreMI);
|
||||
VRM->addSpillSlotUse(StackSlot, StoreMI);
|
||||
DEBUG(dbgs() << "Store:\t" << *StoreMI);
|
||||
|
||||
// If there is a dead store to this stack slot, nuke it now.
|
||||
@ -1500,11 +1541,11 @@ private:
|
||||
SmallVector<unsigned, 2> KillRegs;
|
||||
InvalidateKills(*LastStore, TRI, RegKills, KillOps, &KillRegs);
|
||||
MachineBasicBlock::iterator PrevMII = LastStore;
|
||||
bool CheckDef = PrevMII != MBB.begin();
|
||||
bool CheckDef = PrevMII != MBB->begin();
|
||||
if (CheckDef)
|
||||
--PrevMII;
|
||||
VRM.RemoveMachineInstrFromMaps(LastStore);
|
||||
MBB.erase(LastStore);
|
||||
VRM->RemoveMachineInstrFromMaps(LastStore);
|
||||
MBB->erase(LastStore);
|
||||
if (CheckDef) {
|
||||
// Look at defs of killed registers on the store. Mark the defs
|
||||
// as dead since the store has been deleted and they aren't
|
||||
@ -1515,8 +1556,8 @@ private:
|
||||
MachineInstr *DeadDef = PrevMII;
|
||||
if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
|
||||
// FIXME: This assumes a remat def does not have side effects.
|
||||
VRM.RemoveMachineInstrFromMaps(DeadDef);
|
||||
MBB.erase(DeadDef);
|
||||
VRM->RemoveMachineInstrFromMaps(DeadDef);
|
||||
MBB->erase(DeadDef);
|
||||
++NumDRM;
|
||||
}
|
||||
}
|
||||
@ -1562,14 +1603,14 @@ private:
|
||||
|
||||
/// TransferDeadness - A identity copy definition is dead and it's being
|
||||
/// removed. Find the last def or use and mark it as dead / kill.
|
||||
void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
|
||||
void LocalRewriter::
|
||||
TransferDeadness(unsigned CurDist,
|
||||
unsigned Reg, BitVector &RegKills,
|
||||
std::vector<MachineOperand*> &KillOps,
|
||||
VirtRegMap &VRM) {
|
||||
std::vector<MachineOperand*> &KillOps) {
|
||||
SmallPtrSet<MachineInstr*, 4> Seens;
|
||||
SmallVector<std::pair<MachineInstr*, int>,8> Refs;
|
||||
for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg),
|
||||
RE = RegInfo->reg_end(); RI != RE; ++RI) {
|
||||
for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
|
||||
RE = MRI->reg_end(); RI != RE; ++RI) {
|
||||
MachineInstr *UDMI = &*RI;
|
||||
if (UDMI->getParent() != MBB)
|
||||
continue;
|
||||
@ -1605,7 +1646,7 @@ private:
|
||||
LastUD->setIsDead();
|
||||
break;
|
||||
}
|
||||
VRM.RemoveMachineInstrFromMaps(LastUDMI);
|
||||
VRM->RemoveMachineInstrFromMaps(LastUDMI);
|
||||
MBB->erase(LastUDMI);
|
||||
} else {
|
||||
LastUD->setIsKill();
|
||||
@ -1618,15 +1659,15 @@ private:
|
||||
|
||||
/// rewriteMBB - Keep track of which spills are available even after the
|
||||
/// register allocator is done with them. If possible, avid reloading vregs.
|
||||
void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
|
||||
LiveIntervals *LIs,
|
||||
void
|
||||
LocalRewriter::RewriteMBB(LiveIntervals *LIs,
|
||||
AvailableSpills &Spills, BitVector &RegKills,
|
||||
std::vector<MachineOperand*> &KillOps) {
|
||||
|
||||
DEBUG(dbgs() << "\n**** Local spiller rewriting MBB '"
|
||||
<< MBB.getName() << "':\n");
|
||||
<< MBB->getName() << "':\n");
|
||||
|
||||
MachineFunction &MF = *MBB.getParent();
|
||||
MachineFunction &MF = *MBB->getParent();
|
||||
|
||||
// MaybeDeadStores - When we need to write a value back into a stack slot,
|
||||
// keep track of the inserted store. If the stack slot value is never read
|
||||
@ -1648,46 +1689,45 @@ private:
|
||||
|
||||
unsigned Dist = 0;
|
||||
DistanceMap.clear();
|
||||
for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
|
||||
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
|
||||
MII != E; ) {
|
||||
MachineBasicBlock::iterator NextMII = llvm::next(MII);
|
||||
|
||||
VirtRegMap::MI2VirtMapTy::const_iterator I, End;
|
||||
bool Erased = false;
|
||||
bool BackTracked = false;
|
||||
if (OptimizeByUnfold(MBB, MII,
|
||||
MaybeDeadStores, Spills, RegKills, KillOps, VRM))
|
||||
if (OptimizeByUnfold(MII, MaybeDeadStores, Spills, RegKills, KillOps))
|
||||
NextMII = llvm::next(MII);
|
||||
|
||||
MachineInstr &MI = *MII;
|
||||
|
||||
if (VRM.hasEmergencySpills(&MI)) {
|
||||
if (VRM->hasEmergencySpills(&MI)) {
|
||||
// Spill physical register(s) in the rare case the allocator has run out
|
||||
// of registers to allocate.
|
||||
SmallSet<int, 4> UsedSS;
|
||||
std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI);
|
||||
std::vector<unsigned> &EmSpills = VRM->getEmergencySpills(&MI);
|
||||
for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
|
||||
unsigned PhysReg = EmSpills[i];
|
||||
const TargetRegisterClass *RC =
|
||||
TRI->getPhysicalRegisterRegClass(PhysReg);
|
||||
assert(RC && "Unable to determine register class!");
|
||||
int SS = VRM.getEmergencySpillSlot(RC);
|
||||
int SS = VRM->getEmergencySpillSlot(RC);
|
||||
if (UsedSS.count(SS))
|
||||
llvm_unreachable("Need to spill more than one physical registers!");
|
||||
UsedSS.insert(SS);
|
||||
TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
|
||||
TII->storeRegToStackSlot(*MBB, MII, PhysReg, true, SS, RC);
|
||||
MachineInstr *StoreMI = prior(MII);
|
||||
VRM.addSpillSlotUse(SS, StoreMI);
|
||||
VRM->addSpillSlotUse(SS, StoreMI);
|
||||
|
||||
// Back-schedule reloads and remats.
|
||||
MachineBasicBlock::iterator InsertLoc =
|
||||
ComputeReloadLoc(llvm::next(MII), MBB.begin(), PhysReg, TRI, false,
|
||||
ComputeReloadLoc(llvm::next(MII), MBB->begin(), PhysReg, TRI, false,
|
||||
SS, TII, MF);
|
||||
|
||||
TII->loadRegFromStackSlot(MBB, InsertLoc, PhysReg, SS, RC);
|
||||
TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SS, RC);
|
||||
|
||||
MachineInstr *LoadMI = prior(InsertLoc);
|
||||
VRM.addSpillSlotUse(SS, LoadMI);
|
||||
VRM->addSpillSlotUse(SS, LoadMI);
|
||||
++NumPSpills;
|
||||
DistanceMap.insert(std::make_pair(LoadMI, Dist++));
|
||||
}
|
||||
@ -1695,14 +1735,14 @@ private:
|
||||
}
|
||||
|
||||
// Insert restores here if asked to.
|
||||
if (VRM.isRestorePt(&MI)) {
|
||||
std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
|
||||
if (VRM->isRestorePt(&MI)) {
|
||||
std::vector<unsigned> &RestoreRegs = VRM->getRestorePtRestores(&MI);
|
||||
for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
|
||||
unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
|
||||
if (!VRM.getPreSplitReg(VirtReg))
|
||||
if (!VRM->getPreSplitReg(VirtReg))
|
||||
continue; // Split interval spilled again.
|
||||
unsigned Phys = VRM.getPhys(VirtReg);
|
||||
RegInfo->setPhysRegUsed(Phys);
|
||||
unsigned Phys = VRM->getPhys(VirtReg);
|
||||
MRI->setPhysRegUsed(Phys);
|
||||
|
||||
// Check if the value being restored if available. If so, it must be
|
||||
// from a predecessor BB that fallthrough into this BB. We do not
|
||||
@ -1714,10 +1754,10 @@ private:
|
||||
// ... # r1 not clobbered
|
||||
// ...
|
||||
// = load fi#1
|
||||
bool DoReMat = VRM.isReMaterialized(VirtReg);
|
||||
bool DoReMat = VRM->isReMaterialized(VirtReg);
|
||||
int SSorRMId = DoReMat
|
||||
? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
|
||||
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||
? VRM->getReMatId(VirtReg) : VRM->getStackSlot(VirtReg);
|
||||
const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
|
||||
unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
|
||||
if (InReg == Phys) {
|
||||
// If the value is already available in the expected register, save
|
||||
@ -1749,10 +1789,10 @@ private:
|
||||
|
||||
// Back-schedule reloads and remats.
|
||||
MachineBasicBlock::iterator InsertLoc =
|
||||
ComputeReloadLoc(MII, MBB.begin(), Phys, TRI, DoReMat,
|
||||
ComputeReloadLoc(MII, MBB->begin(), Phys, TRI, DoReMat,
|
||||
SSorRMId, TII, MF);
|
||||
|
||||
TII->copyRegToReg(MBB, InsertLoc, Phys, InReg, RC, RC);
|
||||
TII->copyRegToReg(*MBB, InsertLoc, Phys, InReg, RC, RC);
|
||||
|
||||
// This invalidates Phys.
|
||||
Spills.ClobberPhysReg(Phys);
|
||||
@ -1773,16 +1813,16 @@ private:
|
||||
|
||||
// Back-schedule reloads and remats.
|
||||
MachineBasicBlock::iterator InsertLoc =
|
||||
ComputeReloadLoc(MII, MBB.begin(), Phys, TRI, DoReMat,
|
||||
ComputeReloadLoc(MII, MBB->begin(), Phys, TRI, DoReMat,
|
||||
SSorRMId, TII, MF);
|
||||
|
||||
if (VRM.isReMaterialized(VirtReg)) {
|
||||
ReMaterialize(MBB, InsertLoc, Phys, VirtReg, TII, TRI, VRM);
|
||||
if (VRM->isReMaterialized(VirtReg)) {
|
||||
ReMaterialize(*MBB, InsertLoc, Phys, VirtReg, TII, TRI, *VRM);
|
||||
} else {
|
||||
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||
TII->loadRegFromStackSlot(MBB, InsertLoc, Phys, SSorRMId, RC);
|
||||
const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
|
||||
TII->loadRegFromStackSlot(*MBB, InsertLoc, Phys, SSorRMId, RC);
|
||||
MachineInstr *LoadMI = prior(InsertLoc);
|
||||
VRM.addSpillSlotUse(SSorRMId, LoadMI);
|
||||
VRM->addSpillSlotUse(SSorRMId, LoadMI);
|
||||
++NumLoads;
|
||||
DistanceMap.insert(std::make_pair(LoadMI, Dist++));
|
||||
}
|
||||
@ -1798,23 +1838,24 @@ private:
|
||||
}
|
||||
|
||||
// Insert spills here if asked to.
|
||||
if (VRM.isSpillPt(&MI)) {
|
||||
if (VRM->isSpillPt(&MI)) {
|
||||
std::vector<std::pair<unsigned,bool> > &SpillRegs =
|
||||
VRM.getSpillPtSpills(&MI);
|
||||
VRM->getSpillPtSpills(&MI);
|
||||
for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
|
||||
unsigned VirtReg = SpillRegs[i].first;
|
||||
bool isKill = SpillRegs[i].second;
|
||||
if (!VRM.getPreSplitReg(VirtReg))
|
||||
if (!VRM->getPreSplitReg(VirtReg))
|
||||
continue; // Split interval spilled again.
|
||||
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
|
||||
unsigned Phys = VRM.getPhys(VirtReg);
|
||||
int StackSlot = VRM.getStackSlot(VirtReg);
|
||||
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
|
||||
unsigned Phys = VRM->getPhys(VirtReg);
|
||||
int StackSlot = VRM->getStackSlot(VirtReg);
|
||||
MachineBasicBlock::iterator oldNextMII = llvm::next(MII);
|
||||
TII->storeRegToStackSlot(MBB, llvm::next(MII), Phys, isKill, StackSlot, RC);
|
||||
TII->storeRegToStackSlot(*MBB, llvm::next(MII), Phys, isKill, StackSlot,
|
||||
RC);
|
||||
MachineInstr *StoreMI = prior(oldNextMII);
|
||||
VRM.addSpillSlotUse(StackSlot, StoreMI);
|
||||
VRM->addSpillSlotUse(StackSlot, StoreMI);
|
||||
DEBUG(dbgs() << "Store:\t" << *StoreMI);
|
||||
VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
|
||||
VRM->virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
|
||||
}
|
||||
NextMII = llvm::next(MII);
|
||||
}
|
||||
@ -1832,7 +1873,7 @@ private:
|
||||
if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
|
||||
// Ignore physregs for spilling, but remember that it is used by this
|
||||
// function.
|
||||
RegInfo->setPhysRegUsed(VirtReg);
|
||||
MRI->setPhysRegUsed(VirtReg);
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -1857,16 +1898,16 @@ private:
|
||||
"Not a virtual register?");
|
||||
|
||||
unsigned SubIdx = MI.getOperand(i).getSubReg();
|
||||
if (VRM.isAssignedReg(VirtReg)) {
|
||||
if (VRM->isAssignedReg(VirtReg)) {
|
||||
// This virtual register was assigned a physreg!
|
||||
unsigned Phys = VRM.getPhys(VirtReg);
|
||||
RegInfo->setPhysRegUsed(Phys);
|
||||
unsigned Phys = VRM->getPhys(VirtReg);
|
||||
MRI->setPhysRegUsed(Phys);
|
||||
if (MI.getOperand(i).isDef())
|
||||
ReusedOperands.markClobbered(Phys);
|
||||
substitutePhysReg(MI.getOperand(i), Phys, *TRI);
|
||||
if (VRM.isImplicitlyDefined(VirtReg))
|
||||
if (VRM->isImplicitlyDefined(VirtReg))
|
||||
// FIXME: Is this needed?
|
||||
BuildMI(MBB, &MI, MI.getDebugLoc(),
|
||||
BuildMI(*MBB, &MI, MI.getDebugLoc(),
|
||||
TII->get(TargetOpcode::IMPLICIT_DEF), Phys);
|
||||
continue;
|
||||
}
|
||||
@ -1885,9 +1926,9 @@ private:
|
||||
// interval of r1025. Now suppose both registers are spilled, you can
|
||||
// easily see a situation where both registers are reloaded before
|
||||
// the INSERT_SUBREG and both target registers that would overlap.
|
||||
bool DoReMat = VRM.isReMaterialized(VirtReg);
|
||||
bool DoReMat = VRM->isReMaterialized(VirtReg);
|
||||
int SSorRMId = DoReMat
|
||||
? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
|
||||
? VRM->getReMatId(VirtReg) : VRM->getStackSlot(VirtReg);
|
||||
int ReuseSlot = SSorRMId;
|
||||
|
||||
// Check to see if this stack slot is available.
|
||||
@ -1904,7 +1945,7 @@ private:
|
||||
// fi#1 is available in EDI, but it cannot be reused because it's not in
|
||||
// the right register file.
|
||||
if (PhysReg && !AvoidReload && (SubIdx || MI.isExtractSubreg())) {
|
||||
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||
const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
|
||||
if (!RC->contains(PhysReg))
|
||||
PhysReg = 0;
|
||||
}
|
||||
@ -1935,7 +1976,7 @@ private:
|
||||
DEBUG(dbgs() << " from physreg "
|
||||
<< TRI->getName(PhysReg) << " for vreg"
|
||||
<< VirtReg <<" instead of reloading into physreg "
|
||||
<< TRI->getName(VRM.getPhys(VirtReg)) << '\n');
|
||||
<< TRI->getName(VRM->getPhys(VirtReg)) << '\n');
|
||||
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
||||
MI.getOperand(i).setReg(RReg);
|
||||
MI.getOperand(i).setSubReg(0);
|
||||
@ -1955,7 +1996,7 @@ private:
|
||||
// case, we actually insert a reload for V1 in R1, ensuring that
|
||||
// we can get at R0 or its alias.
|
||||
ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
|
||||
VRM.getPhys(VirtReg), VirtReg);
|
||||
VRM->getPhys(VirtReg), VirtReg);
|
||||
if (isTied)
|
||||
// Only mark it clobbered if this is a use&def operand.
|
||||
ReusedOperands.markClobbered(PhysReg);
|
||||
@ -1994,7 +2035,7 @@ private:
|
||||
// To avoid this problem, and to avoid doing a load right after a store,
|
||||
// we emit a copy from PhysReg into the designated register for this
|
||||
// operand.
|
||||
unsigned DesignatedReg = VRM.getPhys(VirtReg);
|
||||
unsigned DesignatedReg = VRM->getPhys(VirtReg);
|
||||
assert(DesignatedReg && "Must map virtreg to physreg!");
|
||||
|
||||
// Note that, if we reused a register for a previous operand, the
|
||||
@ -2002,9 +2043,9 @@ private:
|
||||
// available. If this occurs, use the register indicated by the
|
||||
// reuser.
|
||||
if (ReusedOperands.hasReuses())
|
||||
DesignatedReg = ReusedOperands.GetRegForReload(VirtReg,
|
||||
DesignatedReg, &MI,
|
||||
Spills, MaybeDeadStores, RegKills, KillOps, VRM);
|
||||
DesignatedReg = ReusedOperands.
|
||||
GetRegForReload(VirtReg, DesignatedReg, &MI, Spills,
|
||||
MaybeDeadStores, RegKills, KillOps, *VRM);
|
||||
|
||||
// If the mapped designated register is actually the physreg we have
|
||||
// incoming, we don't need to inserted a dead copy.
|
||||
@ -2026,16 +2067,16 @@ private:
|
||||
continue;
|
||||
}
|
||||
|
||||
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||
RegInfo->setPhysRegUsed(DesignatedReg);
|
||||
const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
|
||||
MRI->setPhysRegUsed(DesignatedReg);
|
||||
ReusedOperands.markClobbered(DesignatedReg);
|
||||
|
||||
// Back-schedule reloads and remats.
|
||||
MachineBasicBlock::iterator InsertLoc =
|
||||
ComputeReloadLoc(&MI, MBB.begin(), PhysReg, TRI, DoReMat,
|
||||
ComputeReloadLoc(&MI, MBB->begin(), PhysReg, TRI, DoReMat,
|
||||
SSorRMId, TII, MF);
|
||||
|
||||
TII->copyRegToReg(MBB, InsertLoc, DesignatedReg, PhysReg, RC, RC);
|
||||
TII->copyRegToReg(*MBB, InsertLoc, DesignatedReg, PhysReg, RC, RC);
|
||||
|
||||
MachineInstr *CopyMI = prior(InsertLoc);
|
||||
CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
|
||||
@ -2055,7 +2096,7 @@ private:
|
||||
} // if (PhysReg)
|
||||
|
||||
// Otherwise, reload it and remember that we have it.
|
||||
PhysReg = VRM.getPhys(VirtReg);
|
||||
PhysReg = VRM->getPhys(VirtReg);
|
||||
assert(PhysReg && "Must map virtreg to physreg!");
|
||||
|
||||
// Note that, if we reused a register for a previous operand, the
|
||||
@ -2064,25 +2105,25 @@ private:
|
||||
// reuser.
|
||||
if (ReusedOperands.hasReuses())
|
||||
PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
|
||||
Spills, MaybeDeadStores, RegKills, KillOps, VRM);
|
||||
Spills, MaybeDeadStores, RegKills, KillOps, *VRM);
|
||||
|
||||
RegInfo->setPhysRegUsed(PhysReg);
|
||||
MRI->setPhysRegUsed(PhysReg);
|
||||
ReusedOperands.markClobbered(PhysReg);
|
||||
if (AvoidReload)
|
||||
++NumAvoided;
|
||||
else {
|
||||
// Back-schedule reloads and remats.
|
||||
MachineBasicBlock::iterator InsertLoc =
|
||||
ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, DoReMat,
|
||||
ComputeReloadLoc(MII, MBB->begin(), PhysReg, TRI, DoReMat,
|
||||
SSorRMId, TII, MF);
|
||||
|
||||
if (DoReMat) {
|
||||
ReMaterialize(MBB, InsertLoc, PhysReg, VirtReg, TII, TRI, VRM);
|
||||
ReMaterialize(*MBB, InsertLoc, PhysReg, VirtReg, TII, TRI, *VRM);
|
||||
} else {
|
||||
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||
TII->loadRegFromStackSlot(MBB, InsertLoc, PhysReg, SSorRMId, RC);
|
||||
const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
|
||||
TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SSorRMId, RC);
|
||||
MachineInstr *LoadMI = prior(InsertLoc);
|
||||
VRM.addSpillSlotUse(SSorRMId, LoadMI);
|
||||
VRM->addSpillSlotUse(SSorRMId, LoadMI);
|
||||
++NumLoads;
|
||||
DistanceMap.insert(std::make_pair(LoadMI, Dist++));
|
||||
}
|
||||
@ -2118,8 +2159,8 @@ private:
|
||||
if (DeadStore) {
|
||||
DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore);
|
||||
InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
|
||||
VRM.RemoveMachineInstrFromMaps(DeadStore);
|
||||
MBB.erase(DeadStore);
|
||||
VRM->RemoveMachineInstrFromMaps(DeadStore);
|
||||
MBB->erase(DeadStore);
|
||||
MaybeDeadStores[PDSSlot] = NULL;
|
||||
++NumDSE;
|
||||
}
|
||||
@ -2133,7 +2174,7 @@ private:
|
||||
// physical registers that may contain the value of the spilled virtual
|
||||
// register
|
||||
SmallSet<int, 2> FoldedSS;
|
||||
for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
|
||||
for (tie(I, End) = VRM->getFoldedVirts(&MI); I != End; ) {
|
||||
unsigned VirtReg = I->second.first;
|
||||
VirtRegMap::ModRef MR = I->second.second;
|
||||
DEBUG(dbgs() << "Folded vreg: " << VirtReg << " MR: " << MR);
|
||||
@ -2141,7 +2182,7 @@ private:
|
||||
// MI2VirtMap be can updated which invalidate the iterator.
|
||||
// Increment the iterator first.
|
||||
++I;
|
||||
int SS = VRM.getStackSlot(VirtReg);
|
||||
int SS = VRM->getStackSlot(VirtReg);
|
||||
if (SS == VirtRegMap::NO_STACK_SLOT)
|
||||
continue;
|
||||
FoldedSS.insert(SS);
|
||||
@ -2158,8 +2199,8 @@ private:
|
||||
if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
|
||||
DEBUG(dbgs() << "Promoted Load To Copy: " << MI);
|
||||
if (DestReg != InReg) {
|
||||
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
|
||||
TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
|
||||
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
|
||||
TII->copyRegToReg(*MBB, &MI, DestReg, InReg, RC, RC);
|
||||
MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg);
|
||||
unsigned SubIdx = DefMO->getSubReg();
|
||||
// Revisit the copy so we make sure to notice the effects of the
|
||||
@ -2187,8 +2228,8 @@ private:
|
||||
}
|
||||
|
||||
InvalidateKills(MI, TRI, RegKills, KillOps);
|
||||
VRM.RemoveMachineInstrFromMaps(&MI);
|
||||
MBB.erase(&MI);
|
||||
VRM->RemoveMachineInstrFromMaps(&MI);
|
||||
MBB->erase(&MI);
|
||||
Erased = true;
|
||||
goto ProcessNextInst;
|
||||
}
|
||||
@ -2197,10 +2238,10 @@ private:
|
||||
SmallVector<MachineInstr*, 4> NewMIs;
|
||||
if (PhysReg &&
|
||||
TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
|
||||
MBB.insert(MII, NewMIs[0]);
|
||||
MBB->insert(MII, NewMIs[0]);
|
||||
InvalidateKills(MI, TRI, RegKills, KillOps);
|
||||
VRM.RemoveMachineInstrFromMaps(&MI);
|
||||
MBB.erase(&MI);
|
||||
VRM->RemoveMachineInstrFromMaps(&MI);
|
||||
MBB->erase(&MI);
|
||||
Erased = true;
|
||||
--NextMII; // backtrack to the unfolded instruction.
|
||||
BackTracked = true;
|
||||
@ -2231,13 +2272,13 @@ private:
|
||||
// super-register is needed below.
|
||||
if (KillOpnd && !KillOpnd->getSubReg() &&
|
||||
TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
|
||||
MBB.insert(MII, NewMIs[0]);
|
||||
MBB->insert(MII, NewMIs[0]);
|
||||
NewStore = NewMIs[1];
|
||||
MBB.insert(MII, NewStore);
|
||||
VRM.addSpillSlotUse(SS, NewStore);
|
||||
MBB->insert(MII, NewStore);
|
||||
VRM->addSpillSlotUse(SS, NewStore);
|
||||
InvalidateKills(MI, TRI, RegKills, KillOps);
|
||||
VRM.RemoveMachineInstrFromMaps(&MI);
|
||||
MBB.erase(&MI);
|
||||
VRM->RemoveMachineInstrFromMaps(&MI);
|
||||
MBB->erase(&MI);
|
||||
Erased = true;
|
||||
--NextMII;
|
||||
--NextMII; // backtrack to the unfolded instruction.
|
||||
@ -2252,8 +2293,8 @@ private:
|
||||
// If we get here, the store is dead, nuke it now.
|
||||
DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore);
|
||||
InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
|
||||
VRM.RemoveMachineInstrFromMaps(DeadStore);
|
||||
MBB.erase(DeadStore);
|
||||
VRM->RemoveMachineInstrFromMaps(DeadStore);
|
||||
MBB->erase(DeadStore);
|
||||
if (!NewStore)
|
||||
++NumDSE;
|
||||
}
|
||||
@ -2262,7 +2303,7 @@ private:
|
||||
if (NewStore) {
|
||||
// Treat this store as a spill merged into a copy. That makes the
|
||||
// stack slot value available.
|
||||
VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
|
||||
VRM->virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
|
||||
goto ProcessNextInst;
|
||||
}
|
||||
}
|
||||
@ -2283,8 +2324,8 @@ private:
|
||||
assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
|
||||
"Src hasn't been allocated yet?");
|
||||
|
||||
if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot,
|
||||
Spills, RegKills, KillOps, TRI, VRM)) {
|
||||
if (CommuteToFoldReload(MII, VirtReg, SrcReg, StackSlot,
|
||||
Spills, RegKills, KillOps, TRI)) {
|
||||
NextMII = llvm::next(MII);
|
||||
BackTracked = true;
|
||||
goto ProcessNextInst;
|
||||
@ -2330,10 +2371,10 @@ private:
|
||||
TRI->isSubRegister(KillRegs[0], Dst) ||
|
||||
TRI->isSuperRegister(KillRegs[0], Dst));
|
||||
// Last def is now dead.
|
||||
TransferDeadness(&MBB, Dist, Src, RegKills, KillOps, VRM);
|
||||
TransferDeadness(Dist, Src, RegKills, KillOps);
|
||||
}
|
||||
VRM.RemoveMachineInstrFromMaps(&MI);
|
||||
MBB.erase(&MI);
|
||||
VRM->RemoveMachineInstrFromMaps(&MI);
|
||||
MBB->erase(&MI);
|
||||
Erased = true;
|
||||
Spills.disallowClobberPhysReg(VirtReg);
|
||||
goto ProcessNextInst;
|
||||
@ -2360,13 +2401,13 @@ private:
|
||||
}
|
||||
|
||||
unsigned SubIdx = MO.getSubReg();
|
||||
bool DoReMat = VRM.isReMaterialized(VirtReg);
|
||||
bool DoReMat = VRM->isReMaterialized(VirtReg);
|
||||
if (DoReMat)
|
||||
ReMatDefs.insert(&MI);
|
||||
|
||||
// The only vregs left are stack slot definitions.
|
||||
int StackSlot = VRM.getStackSlot(VirtReg);
|
||||
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
|
||||
int StackSlot = VRM->getStackSlot(VirtReg);
|
||||
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
|
||||
|
||||
// If this def is part of a two-address operand, make sure to execute
|
||||
// the store from the correct physical register.
|
||||
@ -2381,17 +2422,17 @@ private:
|
||||
PhysReg = SuperReg;
|
||||
}
|
||||
} else {
|
||||
PhysReg = VRM.getPhys(VirtReg);
|
||||
PhysReg = VRM->getPhys(VirtReg);
|
||||
if (ReusedOperands.isClobbered(PhysReg)) {
|
||||
// Another def has taken the assigned physreg. It must have been a
|
||||
// use&def which got it due to reuse. Undo the reuse!
|
||||
PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
|
||||
Spills, MaybeDeadStores, RegKills, KillOps, VRM);
|
||||
Spills, MaybeDeadStores, RegKills, KillOps, *VRM);
|
||||
}
|
||||
}
|
||||
|
||||
assert(PhysReg && "VR not assigned a physical register?");
|
||||
RegInfo->setPhysRegUsed(PhysReg);
|
||||
MRI->setPhysRegUsed(PhysReg);
|
||||
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
||||
ReusedOperands.markClobbered(RReg);
|
||||
MI.getOperand(i).setReg(RReg);
|
||||
@ -2399,8 +2440,8 @@ private:
|
||||
|
||||
if (!MO.isDead()) {
|
||||
MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
|
||||
SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
|
||||
LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
|
||||
SpillRegToStackSlot(MII, -1, PhysReg, StackSlot, RC, true,
|
||||
LastStore, Spills, ReMatDefs, RegKills, KillOps);
|
||||
NextMII = llvm::next(MII);
|
||||
|
||||
// Check to see if this is a noop copy. If so, eliminate the
|
||||
@ -2411,8 +2452,8 @@ private:
|
||||
++NumDCE;
|
||||
DEBUG(dbgs() << "Removing now-noop copy: " << MI);
|
||||
InvalidateKills(MI, TRI, RegKills, KillOps);
|
||||
VRM.RemoveMachineInstrFromMaps(&MI);
|
||||
MBB.erase(&MI);
|
||||
VRM->RemoveMachineInstrFromMaps(&MI);
|
||||
MBB->erase(&MI);
|
||||
Erased = true;
|
||||
UpdateKills(*LastStore, TRI, RegKills, KillOps);
|
||||
goto ProcessNextInst;
|
||||
@ -2424,8 +2465,8 @@ private:
|
||||
// Delete dead instructions without side effects.
|
||||
if (!Erased && !BackTracked && isSafeToDelete(MI)) {
|
||||
InvalidateKills(MI, TRI, RegKills, KillOps);
|
||||
VRM.RemoveMachineInstrFromMaps(&MI);
|
||||
MBB.erase(&MI);
|
||||
VRM->RemoveMachineInstrFromMaps(&MI);
|
||||
MBB->erase(&MI);
|
||||
Erased = true;
|
||||
}
|
||||
if (!Erased)
|
||||
@ -2439,10 +2480,6 @@ private:
|
||||
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
llvm::VirtRegRewriter* llvm::createVirtRegRewriter() {
|
||||
switch (RewriterOpt) {
|
||||
default: llvm_unreachable("Unreachable!");
|
||||
|
||||
Reference in New Issue
Block a user