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ARM integrated assembler should encoding choice for add/sub imm.

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For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.

rdar://11156277

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-03-30 17:20:40 +00:00
parent 092c5ccf5b
commit 2d30d947ec
2 changed files with 33 additions and 0 deletions
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25
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -6850,6 +6850,31 @@ processInstruction(MCInst &Inst,
return true;
}
break;
case ARM::t2ADDri:
case ARM::t2SUBri: {
// If the destination and first source operand are the same, and
// the flags are compatible with the current IT status, use encoding T2
// instead of T3. For compatibility with the system 'as'. Make sure the
// wide encoding wasn't explicit.
if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
(unsigned)Inst.getOperand(2).getImm() > 255 ||
((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
(inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
(static_cast<ARMOperand*>(Operands[3])->isToken() &&
static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
break;
MCInst TmpInst;
TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
ARM::tADDi8 : ARM::tSUBi8);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(5));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
case ARM::t2ADDrr: {
// If the destination and first source operand are the same, and
// there's no setting of the flags, use encoding T2 instead of T3.

8
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -75,6 +75,8 @@ _func:
adds r1, r2, #0x1f0
add r2, #1
add r0, r0, #32
adds r2, r2, #56
adds r2, #56
@ CHECK: itet eq @ encoding: [0x0a,0xbf]
@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
@ -89,6 +91,8 @@ _func:
@ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71]
@ CHECK: add.w r2, r2, #1 @ encoding: [0x02,0xf1,0x01,0x02]
@ CHECK: add.w r0, r0, #32 @ encoding: [0x00,0xf1,0x20,0x00]
@ CHECK: adds r2, #56 @ encoding: [0x38,0x32]
@ CHECK: adds r2, #56 @ encoding: [0x38,0x32]
@------------------------------------------------------------------------------
@ -2647,6 +2651,8 @@ _func:
subs r1, r2, #0x1f0
sub r2, #1
sub r0, r0, #32
subs r2, r2, #56
subs r2, #56
@ CHECK: itet eq @ encoding: [0x0a,0xbf]
@ CHECK: subeq r1, r2, #4 @ encoding: [0x11,0x1f]
@ -2661,6 +2667,8 @@ _func:
@ CHECK: subs.w r1, r2, #496 @ encoding: [0xb2,0xf5,0xf8,0x71]
@ CHECK: sub.w r2, r2, #1 @ encoding: [0xa2,0xf1,0x01,0x02]
@ CHECK: sub.w r0, r0, #32 @ encoding: [0xa0,0xf1,0x20,0x00]
@ CHECK: subs r2, #56 @ encoding: [0x38,0x3a]
@ CHECK: subs r2, #56 @ encoding: [0x38,0x3a]
@------------------------------------------------------------------------------