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Preliminary support for getting 64-bit integer constants into registers.

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Preliminary support for division. It's gross because you have to initialize
the "Y" register, which is the top 32 bits of the thing you're dividing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12732 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-04-07 04:00:49 +00:00
parent ff8282604a
commit 2d4fa8faac
4 changed files with 108 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
lib/Target/Sparc/InstSelectSimple.cpp
View File

@ -185,12 +185,25 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
return;
}
case cLong: {
unsigned TmpReg = makeAnotherReg (Type::UIntTy);
uint32_t topHalf, bottomHalf;
topHalf = (uint32_t) (CI->getRawValue () >> 32);
bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
return;
}
default:
std::cerr << "Offending constant: " << *C << "\n";
assert (0 && "Can't copy this kind of constant into register yet");
return;
}
}
std::cerr << "Offending constant: " << *C << "\n";
assert (0 && "Can't copy this kind of constant into register yet");
}
@ -275,6 +288,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned ResultReg = makeAnotherReg (I.getType ());
// FIXME: support long, ulong, fp.
switch (I.getOpcode ()) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
@ -283,8 +298,18 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Mul: {
unsigned MulOpcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, MulOpcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
}
case Instruction::Div: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
// Clear out the Y register (top half of LHS of divide)
BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
}
default:

29
lib/Target/Sparc/SparcV8ISelSimple.cpp
View File

@ -185,12 +185,25 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
return;
}
case cLong: {
unsigned TmpReg = makeAnotherReg (Type::UIntTy);
uint32_t topHalf, bottomHalf;
topHalf = (uint32_t) (CI->getRawValue () >> 32);
bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
return;
}
default:
std::cerr << "Offending constant: " << *C << "\n";
assert (0 && "Can't copy this kind of constant into register yet");
return;
}
}
std::cerr << "Offending constant: " << *C << "\n";
assert (0 && "Can't copy this kind of constant into register yet");
}
@ -275,6 +288,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned ResultReg = makeAnotherReg (I.getType ());
// FIXME: support long, ulong, fp.
switch (I.getOpcode ()) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
@ -283,8 +298,18 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Mul: {
unsigned MulOpcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, MulOpcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
}
case Instruction::Div: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
// Clear out the Y register (top half of LHS of divide)
BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
}
default:

29
lib/Target/SparcV8/InstSelectSimple.cpp
View File

@ -185,12 +185,25 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
return;
}
case cLong: {
unsigned TmpReg = makeAnotherReg (Type::UIntTy);
uint32_t topHalf, bottomHalf;
topHalf = (uint32_t) (CI->getRawValue () >> 32);
bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
return;
}
default:
std::cerr << "Offending constant: " << *C << "\n";
assert (0 && "Can't copy this kind of constant into register yet");
return;
}
}
std::cerr << "Offending constant: " << *C << "\n";
assert (0 && "Can't copy this kind of constant into register yet");
}
@ -275,6 +288,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned ResultReg = makeAnotherReg (I.getType ());
// FIXME: support long, ulong, fp.
switch (I.getOpcode ()) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
@ -283,8 +298,18 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Mul: {
unsigned MulOpcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, MulOpcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
}
case Instruction::Div: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
// Clear out the Y register (top half of LHS of divide)
BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
}
default:

29
lib/Target/SparcV8/SparcV8ISelSimple.cpp
View File

@ -185,12 +185,25 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (((uint32_t) CI->getRawValue ()) & 0x03ff);
return;
}
case cLong: {
unsigned TmpReg = makeAnotherReg (Type::UIntTy);
uint32_t topHalf, bottomHalf;
topHalf = (uint32_t) (CI->getRawValue () >> 32);
bottomHalf = (uint32_t) (CI->getRawValue () & 0x0ffffffffULL);
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (topHalf >> 10);
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (topHalf & 0x03ff);
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm (bottomHalf >> 10);
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg).addImm (bottomHalf & 0x03ff);
return;
}
default:
std::cerr << "Offending constant: " << *C << "\n";
assert (0 && "Can't copy this kind of constant into register yet");
return;
}
}
std::cerr << "Offending constant: " << *C << "\n";
assert (0 && "Can't copy this kind of constant into register yet");
}
@ -275,6 +288,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned ResultReg = makeAnotherReg (I.getType ());
// FIXME: support long, ulong, fp.
switch (I.getOpcode ()) {
case Instruction::Add:
BuildMI (BB, V8::ADDrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
@ -283,8 +298,18 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
case Instruction::Mul: {
unsigned MulOpcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, MulOpcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
unsigned Opcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
}
case Instruction::Div: {
unsigned Opcode = I.getType ()->isSigned () ? V8::SDIVrr : V8::UDIVrr;
// Clear out the Y register (top half of LHS of divide)
BuildMI (BB, V8::WRYrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
BuildMI (BB, V8::NOP, 0); // WR may take up to 4 cycles to finish
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, V8::NOP, 0);
BuildMI (BB, Opcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
}
default: