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Add support for 64-bit count leading ones and zeros instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-10-03 21:16:50 +00:00
parent 631d11765b
commit 2d57088ff0
2 changed files with 32 additions and 0 deletions
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15
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -116,6 +116,15 @@ class MoveToLOHI64<bits<6> func, string instr_asm>:
!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
}
// Count Leading Ones/Zeros in Word
class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
!strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
Requires<[HasBitCount]> {
let shamt = 0;
let rt = rd;
}
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
@ -168,6 +177,12 @@ let Uses = [HI64] in
let Uses = [LO64] in
def MFLO64 : MoveFromLOHI64<0x12, "mflo">;
/// Count Leading
def DCLZ : CountLeading64<0x24, "dclz",
[(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
def DCLO : CountLeading64<0x25, "dclo",
[(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//

17
test/CodeGen/Mips/mips64instrs.ll
View File

@ -116,3 +116,20 @@ entry:
ret i64 %rem
}
declare i64 @llvm.ctlz.i64(i64) nounwind readnone
; CHECK: dclz $2, $4
define i64 @f18(i64 %X) nounwind readnone {
entry:
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X)
ret i64 %tmp1
}
; CHECK: dclo $2, $4
define i64 @f19(i64 %X) nounwind readnone {
entry:
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg)
ret i64 %tmp1
}