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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-10 04:33:40 +00:00
remove fastcc (not fastcall) support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34730 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
f39f771b02
commit
2db39b865e
@ -1223,8 +1223,7 @@ X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
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// bytes, which is needed for tail recursion elimination and stack alignment
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// reasons.
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SDOperand
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X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
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bool isFastCall) {
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X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues()-1;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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@ -1250,17 +1249,16 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
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X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
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};
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static const unsigned GPRArgRegs[][2][2] = {
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{{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
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{{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
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{{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
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static const unsigned GPRArgRegs[][2] = {
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{ X86::CL, X86::DL },
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{ X86::CX, X86::DX },
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{ X86::ECX, X86::EDX }
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};
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static const TargetRegisterClass* GPRClasses[3] = {
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X86::GR8RegisterClass, X86::GR16RegisterClass, X86::GR32RegisterClass
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};
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unsigned GPRInd = (isFastCall ? 1 : 0);
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for (unsigned i = 0; i < NumArgs; ++i) {
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MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
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unsigned ArgIncrement = 4;
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@ -1272,8 +1270,7 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
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HowToPassCallArgument(ObjectVT,
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true, // Use as much registers as possible
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NumIntRegs, NumXMMRegs,
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(isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS),
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NumIntRegs, NumXMMRegs, 2,
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ObjSize, ObjIntRegs, ObjXMMRegs);
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if (ObjSize > 4)
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@ -1285,7 +1282,7 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
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case MVT::i8:
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case MVT::i16:
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case MVT::i32: {
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unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][GPRInd][NumIntRegs];
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unsigned RegToUse = GPRArgRegs[ObjectVT-MVT::i8][NumIntRegs];
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Reg = AddLiveIn(MF, RegToUse, GPRClasses[ObjectVT-MVT::i8]);
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ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
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break;
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@ -1296,7 +1293,6 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64: {
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assert(!isFastCall && "Unhandled argument type!");
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Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
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ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
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break;
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@ -1360,7 +1356,6 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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assert(!isFastCall && "Unknown result type");
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MF.addLiveOut(X86::XMM0);
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break;
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}
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@ -1386,17 +1381,15 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
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unsigned NumIntRegs = 0;
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unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
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static const unsigned GPRArgRegs[][2][2] = {
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{{ X86::AL, X86::DL }, { X86::CL, X86::DL }},
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{{ X86::AX, X86::DX }, { X86::CX, X86::DX }},
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{{ X86::EAX, X86::EDX }, { X86::ECX, X86::EDX }}
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static const unsigned GPRArgRegs[][2] = {
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{ X86::CL, X86::DL },
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{ X86::CX, X86::DX },
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{ X86::ECX, X86::EDX }
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};
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static const unsigned XMMArgRegs[] = {
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X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
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};
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bool isFastCall = CC == CallingConv::X86_FastCall;
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unsigned GPRInd = isFastCall ? 1 : 0;
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for (unsigned i = 0; i != NumOps; ++i) {
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SDOperand Arg = Op.getOperand(5+2*i);
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@ -1404,12 +1397,10 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
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default: assert(0 && "Unknown value type!");
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case MVT::i8:
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case MVT::i16:
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case MVT::i32: {
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unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
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if (NumIntRegs < MaxNumIntRegs) {
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case MVT::i32:
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if (NumIntRegs < 2) {
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++NumIntRegs;
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break;
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}
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} // Fall through
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case MVT::f32:
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NumBytes += 4;
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@ -1423,7 +1414,6 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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assert(!isFastCall && "Unknown value type!");
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if (NumXMMRegs < 4)
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NumXMMRegs++;
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else {
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@ -1455,16 +1445,14 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
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default: assert(0 && "Unexpected ValueType for argument!");
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case MVT::i8:
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case MVT::i16:
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case MVT::i32: {
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unsigned MaxNumIntRegs = (isFastCall ? 2 : FASTCC_NUM_INT_ARGS_INREGS);
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if (NumIntRegs < MaxNumIntRegs) {
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unsigned RegToUse =
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GPRArgRegs[Arg.getValueType()-MVT::i8][GPRInd][NumIntRegs];
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RegsToPass.push_back(std::make_pair(RegToUse, Arg));
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++NumIntRegs;
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break;
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}
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} // Fall through
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case MVT::i32:
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if (NumIntRegs < 2) {
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unsigned RegToUse =
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GPRArgRegs[Arg.getValueType()-MVT::i8][NumIntRegs];
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RegsToPass.push_back(std::make_pair(RegToUse, Arg));
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++NumIntRegs;
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break;
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} // Fall through
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case MVT::f32: {
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SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
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PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
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@ -1485,7 +1473,6 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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assert(!isFastCall && "Unexpected ValueType for argument!");
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if (NumXMMRegs < 4) {
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RegsToPass.push_back(std::make_pair(XMMArgRegs[NumXMMRegs], Arg));
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NumXMMRegs++;
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@ -3573,8 +3560,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::Fast:
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if (EnableFastCC)
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return LowerFastCCCallTo(Op, DAG, CallingConv);
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// TODO: Implement fastcc
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// Falls through
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case CallingConv::C:
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case CallingConv::X86_StdCall:
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@ -3601,9 +3587,8 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::Fast:
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if (EnableFastCC) {
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return LowerFastCCArguments(Op, DAG);
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}
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// TODO: implement fastcc.
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// Falls through
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case CallingConv::C:
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return LowerCCCArguments(Op, DAG);
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@ -3612,7 +3597,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
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return LowerCCCArguments(Op, DAG, true);
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case CallingConv::X86_FastCall:
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MF.getInfo<X86FunctionInfo>()->setDecorationStyle(FastCall);
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return LowerFastCCArguments(Op, DAG, true);
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return LowerFastCCArguments(Op, DAG);
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}
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}
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@ -377,8 +377,7 @@ namespace llvm {
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SDOperand LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,unsigned CC);
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// Fast and FastCall Calling Convention implementation.
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SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG,
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bool isFastCall = false);
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SDOperand LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC);
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SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
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@ -412,20 +411,4 @@ namespace llvm {
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};
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}
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// FASTCC_NUM_INT_ARGS_INREGS - This is the max number of integer arguments
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// to pass in registers. 0 is none, 1 is is "use EAX", 2 is "use EAX and
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// EDX". Anything more is illegal.
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//
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// FIXME: The linscan register allocator currently has problem with
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// coalescing. At the time of this writing, whenever it decides to coalesce
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// a physreg with a virtreg, this increases the size of the physreg's live
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// range, and the live range cannot ever be reduced. This causes problems if
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// too many physregs are coaleced with virtregs, which can cause the register
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// allocator to wedge itself.
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//
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// This code triggers this problem more often if we pass args in registers,
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// so disable it until this is fixed.
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//
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#define FASTCC_NUM_INT_ARGS_INREGS 0
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#endif // X86ISELLOWERING_H
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