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https://github.com/c64scene-ar/llvm-6502.git
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Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
5fae2f1dbb
commit
2dc7768d73
@ -936,32 +936,74 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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EmitJump2Table(MI);
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return;
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}
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case ARM::tBR_JTr:
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case ARM::BR_JTr:
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case ARM::BR_JTm: {
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case ARM::tBR_JTr: {
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// Lower and emit the instruction itself, then the jump table following it.
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MCInst TmpInst;
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// FIXME: The branch instruction is really a pseudo. We should xform it
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// explicitly.
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LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
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OutStreamer.EmitInstruction(TmpInst);
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// Output the data for the jump table itself
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EmitJumpTable(MI);
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return;
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}
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case ARM::BR_JTr: {
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// Lower and emit the instruction itself, then the jump table following it.
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// mov pc, target
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::MOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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// Output the data for the jump table itself
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EmitJumpTable(MI);
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return;
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}
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case ARM::BR_JTm: {
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// Lower and emit the instruction itself, then the jump table following it.
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// ldr pc, target
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MCInst TmpInst;
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if (MI->getOperand(1).getReg() == 0) {
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// literal offset
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TmpInst.setOpcode(ARM::LDRi12);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
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} else {
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TmpInst.setOpcode(ARM::LDRrs);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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}
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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// Output the data for the jump table itself
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EmitJumpTable(MI);
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return;
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}
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case ARM::BR_JTadd: {
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// Lower and emit the instruction itself, then the jump table following it.
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// add pc, target, idx
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MCInst AddInst;
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AddInst.setOpcode(ARM::ADDrr);
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AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
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AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::ADDrr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
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// Add predicate operands.
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AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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AddInst.addOperand(MCOperand::CreateReg(0));
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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// Add 's' bit operand (always reg0 for this)
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AddInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(AddInst);
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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// Output the data for the jump table itself
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EmitJumpTable(MI);
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@ -508,6 +508,24 @@ class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
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let Inst{15-12} = Rt; // Rt
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let Inst{7-4} = op;
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}
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class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
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IndexMode im, Format f, InstrItinClass itin, string opc,
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string asm, string cstr, list<dag> pattern>
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: AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
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pattern> {
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// AM3 store w/ two operands: (GPR, am3offset)
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bits<14> offset;
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bits<4> Rt;
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bits<4> Rn;
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let Inst{27-25} = 0b000;
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let Inst{23} = offset{8};
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let Inst{22} = offset{9};
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rt; // Rt
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let Inst{11-8} = offset{7-4}; // imm7_4/zero
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let Inst{7-4} = op;
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let Inst{3-0} = offset{3-0}; // imm3_0/Rm
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}
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// stores
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class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
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@ -1427,29 +1427,21 @@ let isBranch = 1, isTerminator = 1 in {
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let Inst{23-0} = target;
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}
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let isNotDuplicable = 1, isIndirectBranch = 1,
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// FIXME: $imm field is not specified by asm string. Mark as cgonly.
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isCodeGenOnly = 1 in {
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def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "mov\tpc, $target$jt",
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let isNotDuplicable = 1, isIndirectBranch = 1 in {
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def BR_JTr : ARMPseudoInst<(outs),
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(ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
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IIC_Br,// "mov\tpc, $target$jt",
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[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
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let Inst{11-4} = 0b00000000;
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let Inst{15-12} = 0b1111;
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let Inst{20} = 0; // S Bit
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let Inst{24-21} = 0b1101;
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let Inst{27-25} = 0b000;
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let SZ = SizeSpecial;
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}
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def BR_JTm : JTI<(outs),
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// FIXME: This shouldn't use the generic "addrmode2," but rather be split
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// into i12 and rs suffixed versions.
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def BR_JTm : ARMPseudoInst<(outs),
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(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "ldr\tpc, $target$jt",
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IIC_Br,
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[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
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imm:$id)]> {
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let Inst{15-12} = 0b1111;
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-25} = 0b011;
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let SZ = SizeSpecial;
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}
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def BR_JTadd : ARMPseudoInst<(outs),
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(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
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@ -1730,19 +1722,19 @@ def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
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[(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
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GPR:$Rn, am2offset:$offset))]>;
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def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am3offset:$offset),
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StMiscFrm, IIC_iStore_ru,
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"strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb,
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(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
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def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
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IndexModePre, StMiscFrm, IIC_iStore_ru,
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"strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
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[(set GPR:$Rn_wb,
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(pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
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def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am3offset:$offset),
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StMiscFrm, IIC_iStore_bh_ru,
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"strh", "\t$src, [$base], $offset", "$base = $base_wb",
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[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
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GPR:$base, am3offset:$offset))]>;
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def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
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IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
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"strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
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[(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
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GPR:$Rn, am3offset:$offset))]>;
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// For disassembly only
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def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
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