From 2dd3e1b435fb16f72d4bc671e67db68f55abb2c7 Mon Sep 17 00:00:00 2001 From: Brian Gaeke Date: Sat, 22 Nov 2003 05:18:35 +0000 Subject: [PATCH] Stub for constant shift expr support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10168 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/InstSelectSimple.cpp | 23 +++++++++++++++++++++++ lib/Target/X86/X86ISelSimple.cpp | 23 +++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 1616ec1f982..81a31065300 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -224,6 +224,13 @@ namespace { MachineBasicBlock::iterator &IP, Value *Op0, Value *Op1, unsigned Opcode, unsigned TargetReg); + + /// emitShiftOperation - Common code shared between visitShiftInst and + /// constant expression support. + void emitShiftOperation(MachineBasicBlock *BB, + MachineBasicBlock::iterator &IP, + Value *Op0, Value *Op1, unsigned Opcode, + unsigned TargetReg); /// copyConstantToRegister - Output the instructions required to put the @@ -384,6 +391,12 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB, CE->getOpcode(), R); return; + case Instruction::Shl: + case Instruction::Shr: + emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1), + CE->getOpcode(), R); + break; + default: std::cerr << "Offending expr: " << C << "\n"; assert(0 && "Constant expression not yet handled!\n"); @@ -1568,6 +1581,16 @@ void ISel::visitShiftInst(ShiftInst &I) { } } +/// emitShiftOperation - Common code shared between visitShiftInst and +/// constant expression support. +void ISel::emitShiftOperation(MachineBasicBlock *MBB, + MachineBasicBlock::iterator &IP, + Value *Op0, Value *Op1, unsigned Opcode, + unsigned TargetReg) { + // FIXME: Should do all the stuff from visitShiftInst, but use BMI + assert (0 && "Constant shift operations not yet handled"); +} + /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov' /// instruction. The load and store instructions are the only place where we diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 1616ec1f982..81a31065300 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -224,6 +224,13 @@ namespace { MachineBasicBlock::iterator &IP, Value *Op0, Value *Op1, unsigned Opcode, unsigned TargetReg); + + /// emitShiftOperation - Common code shared between visitShiftInst and + /// constant expression support. + void emitShiftOperation(MachineBasicBlock *BB, + MachineBasicBlock::iterator &IP, + Value *Op0, Value *Op1, unsigned Opcode, + unsigned TargetReg); /// copyConstantToRegister - Output the instructions required to put the @@ -384,6 +391,12 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB, CE->getOpcode(), R); return; + case Instruction::Shl: + case Instruction::Shr: + emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1), + CE->getOpcode(), R); + break; + default: std::cerr << "Offending expr: " << C << "\n"; assert(0 && "Constant expression not yet handled!\n"); @@ -1568,6 +1581,16 @@ void ISel::visitShiftInst(ShiftInst &I) { } } +/// emitShiftOperation - Common code shared between visitShiftInst and +/// constant expression support. +void ISel::emitShiftOperation(MachineBasicBlock *MBB, + MachineBasicBlock::iterator &IP, + Value *Op0, Value *Op1, unsigned Opcode, + unsigned TargetReg) { + // FIXME: Should do all the stuff from visitShiftInst, but use BMI + assert (0 && "Constant shift operations not yet handled"); +} + /// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov' /// instruction. The load and store instructions are the only place where we