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Stub for constant shift expr support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10168 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -224,6 +224,13 @@ namespace {
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MachineBasicBlock::iterator &IP,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg);
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unsigned TargetReg);
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/// emitShiftOperation - Common code shared between visitShiftInst and
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/// constant expression support.
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void emitShiftOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg);
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/// copyConstantToRegister - Output the instructions required to put the
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/// copyConstantToRegister - Output the instructions required to put the
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@ -384,6 +391,12 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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CE->getOpcode(), R);
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CE->getOpcode(), R);
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return;
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return;
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case Instruction::Shl:
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case Instruction::Shr:
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emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode(), R);
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break;
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default:
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default:
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std::cerr << "Offending expr: " << C << "\n";
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expression not yet handled!\n");
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assert(0 && "Constant expression not yet handled!\n");
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@ -1568,6 +1581,16 @@ void ISel::visitShiftInst(ShiftInst &I) {
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}
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}
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}
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}
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/// emitShiftOperation - Common code shared between visitShiftInst and
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/// constant expression support.
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void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg) {
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// FIXME: Should do all the stuff from visitShiftInst, but use BMI
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assert (0 && "Constant shift operations not yet handled");
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}
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/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
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/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
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/// instruction. The load and store instructions are the only place where we
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/// instruction. The load and store instructions are the only place where we
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@ -224,6 +224,13 @@ namespace {
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MachineBasicBlock::iterator &IP,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg);
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unsigned TargetReg);
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/// emitShiftOperation - Common code shared between visitShiftInst and
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/// constant expression support.
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void emitShiftOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg);
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/// copyConstantToRegister - Output the instructions required to put the
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/// copyConstantToRegister - Output the instructions required to put the
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@ -384,6 +391,12 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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CE->getOpcode(), R);
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CE->getOpcode(), R);
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return;
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return;
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case Instruction::Shl:
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case Instruction::Shr:
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emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
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CE->getOpcode(), R);
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break;
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default:
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default:
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std::cerr << "Offending expr: " << C << "\n";
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expression not yet handled!\n");
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assert(0 && "Constant expression not yet handled!\n");
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@ -1568,6 +1581,16 @@ void ISel::visitShiftInst(ShiftInst &I) {
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}
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}
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}
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}
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/// emitShiftOperation - Common code shared between visitShiftInst and
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/// constant expression support.
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void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg) {
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// FIXME: Should do all the stuff from visitShiftInst, but use BMI
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assert (0 && "Constant shift operations not yet handled");
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}
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/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
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/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
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/// instruction. The load and store instructions are the only place where we
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/// instruction. The load and store instructions are the only place where we
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