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AVX-512: Fixed size of mask registers

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201546 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2014-02-18 07:52:26 +00:00
parent 47f6b173f5
commit 2e58f4605d
1 changed files with 6 additions and 4 deletions
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10
lib/Target/X86/X86RegisterInfo.td
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@ -463,11 +463,13 @@ def VR128X : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
256, (sequence "YMM%u", 0, 31)>;
def VK1 : RegisterClass<"X86", [i1], 1, (sequence "K%u", 0, 7)>;
def VK8 : RegisterClass<"X86", [v8i1], 8, (sequence "K%u", 0, 7)>;
// The size of the all masked registers is 16 bit because we have only one
// KMOVW istruction that can store this register in memory, and it writes 2 bytes
def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)>;
def VK8 : RegisterClass<"X86", [v8i1], 16, (sequence "K%u", 0, 7)>;
def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)>;
def VK1WM : RegisterClass<"X86", [i1], 1, (sub VK1, K0)>;
def VK8WM : RegisterClass<"X86", [v8i1], 8, (sub VK8, K0)>;
def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)>;
def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)>;
def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>;