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Use stdint macros for specifying size of constants

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211231 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-06-18 22:11:03 +00:00
parent fb2b9fb894
commit 2ea6d93c5e
1 changed files with 3 additions and 2 deletions
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5
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -1636,7 +1636,7 @@ SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
DAG.getConstant(1023, MVT::i32));
// Extract the sign bit.
const SDValue SignBitMask = DAG.getConstant(1ul << 31, MVT::i32);
const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
// Extend back to to 64-bits.
@ -1645,7 +1645,8 @@ SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
const SDValue FractMask = DAG.getConstant((1LL << FractBits) - 1, MVT::i64);
const SDValue FractMask
= DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);