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[ARM] Use FileCheck instead of grep for ARM LDRD negative tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191683 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2013-09-30 17:31:26 +00:00
parent c13c9e5a9d
commit 2f184eaf89
1 changed files with 42 additions and 19 deletions
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61
test/MC/ARM/arm-ldrd.s
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@ -1,34 +1,57 @@
// RUN: not llvm-mc -arch arm -mattr=+v5te \
// RUN: < %s >/dev/null 2> %t
// RUN: grep "error: Rt must be even-numbered" %t | count 7
// RUN: grep "error: Rt can't be R14" %t | count 7
// RUN: grep "error: destination operands must be sequential" %t | count 7
// RUN: grep "error: base register needs to be different from destination registers" %t | count 4
// RUN: not llvm-mc -arch arm -mattr=+v5te %s 2>&1 | FileCheck %s
//
// rdar://14479793
ldrd r1, r2, [pc, #0]
ldrd lr, pc, [pc, #0]
ldrd r0, r3, [pc, #0]
ldrd r1, r2, [r3, #4]
ldrd lr, pc, [r3, #4]
ldrd r0, r3, [r4, #4]
ldrd r1, r2, [r3], #4
ldrd lr, pc, [r3], #4
ldrd r0, r3, [r4], #4
ldrd r1, r2, [r3, #4]!
ldrd lr, pc, [r3, #4]!
ldrd r0, r3, [r4, #4]!
ldrd r1, r2, [r3, -r4]!
ldrd lr, pc, [r3, -r4]!
ldrd r0, r3, [r4, -r5]!
ldrd r1, r2, [r3, r4]
ldrd lr, pc, [r3, r4]
ldrd r0, r3, [r4, r5]
ldrd r1, r2, [r3], r4
ldrd lr, pc, [r3], r4
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
// CHECK: error: Rt must be even-numbered
ldrd r0, r3, [pc, #0]
ldrd r0, r3, [r4, #4]
ldrd r0, r3, [r4], #4
ldrd r0, r3, [r4, #4]!
ldrd r0, r3, [r4, -r5]!
ldrd r0, r3, [r4, r5]
ldrd r0, r3, [r4], r5
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
// CHECK: error: destination operands must be sequential
ldrd lr, pc, [pc, #0]
ldrd lr, pc, [r3, #4]
ldrd lr, pc, [r3], #4
ldrd lr, pc, [r3, #4]!
ldrd lr, pc, [r3, -r4]!
ldrd lr, pc, [r3, r4]
ldrd lr, pc, [r3], r4
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
// CHECK: error: Rt can't be R14
ldrd r0, r1, [r0], #4
ldrd r0, r1, [r1], #4
ldrd r0, r1, [r0, #4]!
ldrd r0, r1, [r1, #4]!
// CHECK: error: base register needs to be different from destination registers
// CHECK: error: base register needs to be different from destination registers
// CHECK: error: base register needs to be different from destination registers
// CHECK: error: base register needs to be different from destination registers