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Add support for the convergent flag at the MC and MachineInstr levels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238450 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -483,6 +483,13 @@ public:
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return hasProperty(MCID::NotDuplicable, Type);
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}
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/// Return true if this instruction is convergent.
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/// Convergent instructions can only be moved to locations that are
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/// control-equivalent to their initial position.
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bool isConvergent(QueryType Type = AnyInBundle) const {
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return hasProperty(MCID::Convergent, Type);
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}
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/// Returns true if the specified instruction has a delay slot
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/// which must be filled by the code generator.
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bool hasDelaySlot(QueryType Type = AnyInBundle) const {
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@@ -125,7 +125,8 @@ enum Flag {
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ExtraDefRegAllocReq,
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RegSequence,
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ExtractSubreg,
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InsertSubreg
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InsertSubreg,
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Convergent
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};
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}
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@@ -331,6 +332,13 @@ public:
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/// override accordingly.
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bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); }
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/// \brief Return true if this instruction is convergent.
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///
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/// Convergent instructions may only be moved to locations that are
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/// control-equivalent to their original positions.
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bool isConvergent() const { return Flags & (1 << MCID::Convergent); }
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//===--------------------------------------------------------------------===//
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// Side Effect Analysis
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//===--------------------------------------------------------------------===//
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@@ -381,6 +381,7 @@ class Instruction {
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bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
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bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
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bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
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bit isConvergent = 0; // Is this instruction convergent?
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bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
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bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
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bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
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