Add support for the convergent flag at the MC and MachineInstr levels.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238450 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2015-05-28 18:33:39 +00:00
parent 4c9279423e
commit 2f6ca834ff
6 changed files with 51 additions and 32 deletions

View File

@@ -125,7 +125,8 @@ enum Flag {
ExtraDefRegAllocReq,
RegSequence,
ExtractSubreg,
InsertSubreg
InsertSubreg,
Convergent
};
}
@@ -331,6 +332,13 @@ public:
/// override accordingly.
bool isInsertSubregLike() const { return Flags & (1 << MCID::InsertSubreg); }
/// \brief Return true if this instruction is convergent.
///
/// Convergent instructions may only be moved to locations that are
/// control-equivalent to their original positions.
bool isConvergent() const { return Flags & (1 << MCID::Convergent); }
//===--------------------------------------------------------------------===//
// Side Effect Analysis
//===--------------------------------------------------------------------===//