Replace copy-pasted debug value skipping with MBB::getLastNonDebugInstr

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240639 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -96,15 +96,10 @@ bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
                                    SmallVectorImpl<MachineOperand> &Cond,
                                    bool AllowModify) const {
   // If the block has no terminators, it just falls into the block after it.
-  MachineBasicBlock::iterator I = MBB.end();
+  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
-  if (I == MBB.begin())
+  if (I == MBB.end())
     return false;
-  --I;
+
-  while (I->isDebugValue()) {
-    if (I == MBB.begin())
-      return false;
-    --I;
-  }
   if (!isUnpredicatedTerminator(I))
     return false;
 
@@ -224,15 +219,10 @@ bool AArch64InstrInfo::ReverseBranchCondition(
 }
 
 unsigned AArch64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
-  MachineBasicBlock::iterator I = MBB.end();
+  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
-  if (I == MBB.begin())
+  if (I == MBB.end())
     return 0;
-  --I;
+
-  while (I->isDebugValue()) {
-    if (I == MBB.begin())
-      return 0;
-    --I;
-  }
   if (!isUncondBranchOpcode(I->getOpcode()) &&
       !isCondBranchOpcode(I->getOpcode()))
     return 0;

lib/Target/AMDGPU/R600InstrInfo.cpp

@@ -697,15 +697,10 @@ R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
   // Most of the following comes from the ARM implementation of AnalyzeBranch
 
   // If the block has no terminators, it just falls into the block after it.
-  MachineBasicBlock::iterator I = MBB.end();
+  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
-  if (I == MBB.begin())
+  if (I == MBB.end())
     return false;
-  --I;
+
-  while (I->isDebugValue()) {
-    if (I == MBB.begin())
-      return false;
-    --I;
-  }
   // AMDGPU::BRANCH* instructions are only available after isel and are not
   // handled
   if (isBranch(I->getOpcode()))

lib/Target/ARM/ARMBaseInstrInfo.cpp

@@ -367,14 +367,10 @@ ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
 
 
 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
-  MachineBasicBlock::iterator I = MBB.end();
+  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
-  if (I == MBB.begin()) return 0;
+  if (I == MBB.end())
-  --I;
+    return 0;
-  while (I->isDebugValue()) {
+
-    if (I == MBB.begin())
-      return 0;
-    --I;
-  }
   if (!isUncondBranchOpcode(I->getOpcode()) &&
       !isCondBranchOpcode(I->getOpcode()))
     return 0;

lib/Target/XCore/XCoreInstrInfo.cpp

@@ -196,15 +196,10 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                               SmallVectorImpl<MachineOperand> &Cond,
                               bool AllowModify) const {
   // If the block has no terminators, it just falls into the block after it.
-  MachineBasicBlock::iterator I = MBB.end();
+  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
-  if (I == MBB.begin())
+  if (I == MBB.end())
     return false;
-  --I;
+
-  while (I->isDebugValue()) {
-    if (I == MBB.begin())
-      return false;
-    --I;
-  }
   if (!isUnpredicatedTerminator(I))
     return false;
 
@@ -312,14 +307,10 @@ XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
 
 unsigned
 XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
-  MachineBasicBlock::iterator I = MBB.end();
+  MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
-  if (I == MBB.begin()) return 0;
+  if (I == MBB.end())
-  --I;
+    return 0;
-  while (I->isDebugValue()) {
+
-    if (I == MBB.begin())
-      return 0;
-    --I;
-  }
   if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
     return 0;