mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-14 22:38:03 +00:00
Minor cleanup; fixes review comments for a previous patch. Sorry for
taking so long to get to this! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73757 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
9683f18174
commit
2fb070bf5a
@ -95,14 +95,13 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
|
||||
if (InVT.isVector() && OutVT.isInteger()) {
|
||||
// Handle cases like i64 = BIT_CONVERT v1i64 on x86, where the operand
|
||||
// is legal but the result is not.
|
||||
MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OutVT), 2);
|
||||
MVT NVT = MVT::getVectorVT(NOutVT, 2);
|
||||
|
||||
if (isTypeLegal(NVT)) {
|
||||
SDValue CastInOp = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, InOp);
|
||||
MVT EltNVT = NVT.getVectorElementType();
|
||||
Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltNVT, CastInOp,
|
||||
Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NOutVT, CastInOp,
|
||||
DAG.getIntPtrConstant(0));
|
||||
Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltNVT, CastInOp,
|
||||
Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NOutVT, CastInOp,
|
||||
DAG.getIntPtrConstant(1));
|
||||
|
||||
if (TLI.isBigEndian())
|
||||
|
Loading…
x
Reference in New Issue
Block a user