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Add dummy 'm' inline asm constraint handler for Sparc. I'm not sure, whether it is correct, however :)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57345 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2008-10-10 10:14:47 +00:00
parent a43e51d0fe
commit 2fcfd83cb4
1 changed files with 26 additions and 0 deletions
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26
lib/Target/Sparc/SparcISelDAGToDAG.cpp
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@ -45,6 +45,12 @@ public:
bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset);
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps);
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelect();
@ -184,6 +190,26 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
}
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool
SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps) {
SDValue Op0, Op1;
switch (ConstraintCode) {
default: return true;
case 'm': // memory
if (!SelectADDRrr(Op, Op, Op0, Op1))
SelectADDRri(Op, Op, Op0, Op1);
break;
}
OutOps.push_back(Op0);
OutOps.push_back(Op1);
return false;
}
/// createSparcISelDag - This pass converts a legalized DAG into a
/// SPARC-specific DAG, ready for instruction scheduling.
///