6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-23 01:24:30 +00:00
Code Issues Projects Releases Wiki Activity

Do not replace operands of pseudo instructions with register $zero.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156663 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2012-05-11 23:22:18 +00:00
parent aefd36bdda
commit 3011a33a63
2 changed files with 18 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -213,7 +213,8 @@ bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
MachineInstr *MI = MO.getParent(); MachineInstr *MI = MO.getParent();
// Do not replace if it is a phi's operand or is tied to def operand. // Do not replace if it is a phi's operand or is tied to def operand.
if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo())) if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) ||
MI->isPseudo())
continue; continue;
MO.setReg(ZeroReg); MO.setReg(ZeroReg);

16
test/CodeGen/Mips/atomic.ll
View File

@ -242,3 +242,19 @@ entry:
; CHECK: sync 0 ; CHECK: sync 0
} }
; make sure that this assertion in
; TwoAddressInstructionPass::TryInstructionTransform does not fail:
;
; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) &&
;
; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an
; operand of an atomic instruction with register $zero.
@a = external global i32
define i32 @zeroreg() nounwind {
entry:
%0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst
%1 = icmp eq i32 %0, 1
%conv = zext i1 %1 to i32
ret i32 %conv
}