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Define instructions for cmovo and cmovno.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61836 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2009-01-07 00:35:10 +00:00
parent 653456c351
commit 305fceb56c
3 changed files with 90 additions and 9 deletions
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20
lib/Target/X86/X86Instr64bit.td
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@ -1004,6 +1004,16 @@ def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
"cmovnp\t{$src2, $dst|$dst, $src2}", "cmovnp\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2, [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
X86_COND_NP, EFLAGS))]>, TB; X86_COND_NP, EFLAGS))]>, TB;
def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
"cmovo\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
X86_COND_O, EFLAGS))]>, TB;
def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
"cmovno\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
X86_COND_NO, EFLAGS))]>, TB;
} // isCommutable = 1 } // isCommutable = 1
def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64] def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
@ -1076,6 +1086,16 @@ def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
"cmovnp\t{$src2, $dst|$dst, $src2}", "cmovnp\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
X86_COND_NP, EFLAGS))]>, TB; X86_COND_NP, EFLAGS))]>, TB;
def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
"cmovo\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
X86_COND_O, EFLAGS))]>, TB;
def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
(outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
"cmovno\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
X86_COND_NO, EFLAGS))]>, TB;
} // isTwoAddress } // isTwoAddress
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

17
lib/Target/X86/X86InstrInfo.cpp
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@ -499,6 +499,9 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
{ X86::CMOVNS16rr, X86::CMOVNS16rm }, { X86::CMOVNS16rr, X86::CMOVNS16rm },
{ X86::CMOVNS32rr, X86::CMOVNS32rm }, { X86::CMOVNS32rr, X86::CMOVNS32rm },
{ X86::CMOVNS64rr, X86::CMOVNS64rm }, { X86::CMOVNS64rr, X86::CMOVNS64rm },
{ X86::CMOVO16rr, X86::CMOVO16rm },
{ X86::CMOVO32rr, X86::CMOVO32rm },
{ X86::CMOVO64rr, X86::CMOVO64rm },
{ X86::CMOVP16rr, X86::CMOVP16rm }, { X86::CMOVP16rr, X86::CMOVP16rm },
{ X86::CMOVP32rr, X86::CMOVP32rm }, { X86::CMOVP32rr, X86::CMOVP32rm },
{ X86::CMOVP64rr, X86::CMOVP64rm }, { X86::CMOVP64rr, X86::CMOVP64rm },
@ -1308,7 +1311,13 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
case X86::CMOVP64rr: case X86::CMOVP64rr:
case X86::CMOVNP16rr: case X86::CMOVNP16rr:
case X86::CMOVNP32rr: case X86::CMOVNP32rr:
case X86::CMOVNP64rr: { case X86::CMOVNP64rr:
case X86::CMOVO16rr:
case X86::CMOVO32rr:
case X86::CMOVO64rr:
case X86::CMOVNO16rr:
case X86::CMOVNO32rr:
case X86::CMOVNO64rr: {
unsigned Opc = 0; unsigned Opc = 0;
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: break; default: break;
@ -1354,6 +1363,12 @@ X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
case X86::CMOVO64rr: Opc = X86::CMOVNO32rr; break;
case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
} }
if (NewMI) { if (NewMI) {
MachineFunction &MF = *MI->getParent()->getParent(); MachineFunction &MF = *MI->getParent()->getParent();

62
lib/Target/X86/X86InstrInfo.td
View File

@ -838,7 +838,6 @@ def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
X86_COND_B, EFLAGS))]>, X86_COND_B, EFLAGS))]>,
TB; TB;
def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2), (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"cmovae\t{$src2, $dst|$dst, $src2}", "cmovae\t{$src2, $dst|$dst, $src2}",
@ -995,14 +994,31 @@ def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2, [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
X86_COND_NP, EFLAGS))]>, X86_COND_NP, EFLAGS))]>,
TB; TB;
} // isCommutable = 1 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32] "cmovo\t{$src2, $dst|$dst, $src2}",
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
"cmovnp\t{$src2, $dst|$dst, $src2}", X86_COND_O, EFLAGS))]>,
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), TB, OpSize;
X86_COND_NP, EFLAGS))]>, def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"cmovo\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
X86_COND_O, EFLAGS))]>,
TB; TB;
def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"cmovno\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
X86_COND_NO, EFLAGS))]>,
TB, OpSize;
def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"cmovno\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
X86_COND_NO, EFLAGS))]>,
TB;
} // isCommutable = 1
def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16] def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
@ -1166,6 +1182,36 @@ def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
X86_COND_NP, EFLAGS))]>, X86_COND_NP, EFLAGS))]>,
TB, OpSize; TB, OpSize;
def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
"cmovnp\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
X86_COND_NP, EFLAGS))]>,
TB;
def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
"cmovo\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
X86_COND_O, EFLAGS))]>,
TB, OpSize;
def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
"cmovo\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
X86_COND_O, EFLAGS))]>,
TB;
def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
(outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
"cmovno\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
X86_COND_NO, EFLAGS))]>,
TB, OpSize;
def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
(outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
"cmovno\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
X86_COND_NO, EFLAGS))]>,
TB;
} // Uses = [EFLAGS] } // Uses = [EFLAGS]