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R600/SI: fix VOPC encoding v2

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Previously it only worked because of coincident.

v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0
    for the unused SRC2

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175352 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig 2013-02-16 11:28:07 +00:00
parent 7c52866a14
commit 305fefbb65
1 changed files with 18 additions and 39 deletions
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57
lib/Target/R600/SIInstrFormats.td
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@ -21,26 +21,12 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class VOP3b_2IN <bits<9> op, string opName, RegisterClass dstClass,
RegisterClass src0Class, RegisterClass src1Class,
list<dag> pattern>
: VOP3b <op, (outs dstClass:$vdst),
(ins src0Class:$src0, src1Class:$src1, InstFlag:$src2, InstFlag:$sdst,
InstFlag:$omod, InstFlag:$neg),
opName, pattern
>;
class VOP3_1_32 <bits<9> op, string opName, list<dag> pattern>
: VOP3b_2IN <op, opName, SReg_1, AllReg_32, VReg_32, pattern>;
class VOP3_32 <bits<9> op, string opName, list<dag> pattern> class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
: VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>; : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
: VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>; : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
class SOP1_32 <bits<8> op, string opName, list<dag> pattern> class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
: SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>; : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
@ -109,35 +95,28 @@ class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
class SOPK_64 <bits<5> op, string opName, list<dag> pattern> class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
: SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>; : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
string opName, list<dag> pattern> : string opName, list<dag> pattern> {
VOPC <
op, (ins arc:$src0, vrc:$src1), opName, pattern
>;
multiclass VOPC_32 <bits<9> op, string opName, list<dag> pattern> { def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>;
def _e64 : VOP3 <
def _e32 : VOPC_Helper <
{op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
VReg_32, AllReg_32, opName, pattern
>;
def _e64 : VOP3_1_32 <
op,
opName, pattern
>;
}
multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> {
def _e32 : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>;
def _e64 : VOP3_64 <
{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
opName, [] (outs SReg_1:$dst),
>; (ins arc:$src0, vrc:$src1,
InstFlag:$abs, InstFlag:$clamp,
InstFlag:$omod, InstFlag:$neg),
opName, pattern
> {
let SRC2 = 0x80;
}
} }
multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern>
: VOPC_Helper <op, VReg_32, AllReg_32, opName, pattern>;
multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern>
: VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>;
class SOPC_32 <bits<7> op, string opName, list<dag> pattern> class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
: SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>; : SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;