6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-09 01:38:03 +00:00
Code Issues Projects Releases Wiki Activity

ARM: optimization for sub+abs.

Browse Source 
This patch will optimize abs(x-y)
FROM
sub, movs, rsbmi
TO
subs, rsbmi

For abs, we will use cmp instead of movs. This is necessary because we already
have an existing peephole pass which optimizes away cmp following sub.

rdar: 11633193


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158551 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren 2012-06-15 21:32:12 +00:00
parent 695fd1a455
commit 307473dec0
3 changed files with 27 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -6808,9 +6808,6 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineRegisterInfo &MRI = Fn->getRegInfo();
// In Thumb mode S must not be specified if source register is the SP or
// PC and if destination register is the SP, so restrict register class
unsigned NewMovDstReg = MRI.createVirtualRegister(isThumb2 ?
(const TargetRegisterClass*)&ARM::rGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass);
unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
(const TargetRegisterClass*)&ARM::rGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass);
@ -6827,12 +6824,10 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// fall through to SinkMBB
RSBBB->addSuccessor(SinkBB);
// insert a movs at the end of BB
BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr),
NewMovDstReg)
.addReg(ABSSrcReg, RegState::Kill)
.addImm((unsigned)ARMCC::AL).addReg(0)
.addReg(ARM::CPSR, RegState::Define);
// insert a cmp at the end of BB
AddDefaultPred(BuildMI(BB, dl,
TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
.addReg(ABSSrcReg).addImm(0));
// insert a bcc with opposite CC to ARMCC::MI at the end of BB
BuildMI(BB, dl,
@ -6844,7 +6839,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// by if-conversion pass
BuildMI(*RSBBB, RSBBB->begin(), dl,
TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
.addReg(NewMovDstReg, RegState::Kill)
.addReg(ABSSrcReg, RegState::Kill)
.addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
// insert PHI in SinkBB,
@ -6852,7 +6847,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
BuildMI(*SinkBB, SinkBB->begin(), dl,
TII->get(ARM::PHI), ABSDstReg)
.addReg(NewRsbDstReg).addMBB(RSBBB)
.addReg(NewMovDstReg).addMBB(BB);
.addReg(ABSSrcReg).addMBB(BB);
// remove ABS instruction
MI->eraseFromParent();

20
test/CodeGen/ARM/iabs.ll
View File

@ -10,7 +10,25 @@ define i32 @test(i32 %a) {
%b = icmp sgt i32 %a, -1
%abs = select i1 %b, i32 %a, i32 %tmp1neg
ret i32 %abs
; CHECK: movs r0, r0
; CHECK: cmp
; CHECK: rsbmi r0, r0, #0
; CHECK: bx lr
}
; rdar://11633193
;; 3 instructions will be generated for abs(a-b):
;; subs
;; rsbmi
;; bx
define i32 @test2(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK: test2
; CHECK: subs
; CHECK-NEXT: rsbmi
; CHECK-NEXT: bx
%sub = sub nsw i32 %a, %b
%cmp = icmp sgt i32 %sub, -1
%sub1 = sub nsw i32 0, %sub
%cond = select i1 %cmp, i32 %sub, i32 %sub1
ret i32 %cond
}

4
test/CodeGen/ARM/thumb2-it-block.ll
View File

@ -3,10 +3,10 @@
define i32 @test(i32 %a, i32 %b) {
entry:
; CHECK: movs.w
; CHECK: cmp
; CHECK-NEXT: it mi
; CHECK-NEXT: rsbmi
; CHECK-NEXT: movs.w
; CHECK-NEXT: cmp
; CHECK-NEXT: it mi
; CHECK-NEXT: rsbmi
%cmp1 = icmp slt i32 %a, 0