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Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2009-10-08 18:56:10 +00:00
parent cd7e327cdf
commit 30aea9d96e
4 changed files with 126 additions and 12 deletions
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65
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@@ -1510,18 +1510,67 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue MemAddr, MemUpdate, MemOpc;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
return NULL;
if (VT.is64BitVector()) {
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld2lane type");
case MVT::v8i8: Opc = ARM::VLD2LNd8; break;
case MVT::v4i16: Opc = ARM::VLD2LNd16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2LNd32; break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4),
N->getOperand(5), Chain };
return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7);
}
// Quad registers are handled by extracting subregs, doing the load,
// and then inserting the results as subregs.
EVT RegVT;
unsigned Opc2 = 0;
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld2lane type");
case MVT::v8i8: Opc = ARM::VLD2LNd8; break;
case MVT::v4i16: Opc = ARM::VLD2LNd16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2LNd32; break;
case MVT::v8i16:
Opc = ARM::VLD2LNq16a;
Opc2 = ARM::VLD2LNq16b;
RegVT = MVT::v4i16;
break;
case MVT::v4f32:
Opc = ARM::VLD2LNq32a;
Opc2 = ARM::VLD2LNq32b;
RegVT = MVT::v2f32;
break;
case MVT::v4i32:
Opc = ARM::VLD2LNq32a;
Opc2 = ARM::VLD2LNq32b;
RegVT = MVT::v2i32;
break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4),
N->getOperand(5), Chain };
return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7);
unsigned Lane = cast<ConstantSDNode>(N->getOperand(5))->getZExtValue();
unsigned NumElts = RegVT.getVectorNumElements();
int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
N->getOperand(3));
SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
N->getOperand(4));
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1,
getI32Imm(Lane % NumElts), Chain };
SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
dl, RegVT, RegVT, MVT::Other,
Ops, 7);
SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
N->getOperand(3),
SDValue(VLdLn, 0));
SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
N->getOperand(4),
SDValue(VLdLn, 1));
Chain = SDValue(VLdLn, 2);
ReplaceUses(SDValue(N, 0), Q0);
ReplaceUses(SDValue(N, 1), Q1);
ReplaceUses(SDValue(N, 2), Chain);
return NULL;
}
case Intrinsic::arm_neon_vld3lane: {

16
lib/Target/ARM/ARMInstrNEON.td
View File

@@ -266,16 +266,24 @@ def VLD4q32b : VLD4WB<0b1000, "vld4.32">;
// FIXME: Not yet implemented.
// VLD2LN : Vector Load (single 2-element structure to one lane)
class VLD2LND<bits<4> op11_8, string OpcodeStr>
class VLD2LN<bits<4> op11_8, string OpcodeStr>
: NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
IIC_VLD2,
!strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
"$src1 = $dst1, $src2 = $dst2", []>;
def VLD2LNd8 : VLD2LND<0b0001, "vld2.8">;
def VLD2LNd16 : VLD2LND<0b0101, "vld2.16">;
def VLD2LNd32 : VLD2LND<0b1001, "vld2.32">;
def VLD2LNd8 : VLD2LN<0b0001, "vld2.8">;
def VLD2LNd16 : VLD2LN<0b0101, "vld2.16">;
def VLD2LNd32 : VLD2LN<0b1001, "vld2.32">;
// vld2 to double-spaced even registers.
def VLD2LNq16a: VLD2LN<0b0101, "vld2.16">;
def VLD2LNq32a: VLD2LN<0b1001, "vld2.32">;
// vld2 to double-spaced odd registers.
def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">;
def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">;
// VLD3LN : Vector Load (single 3-element structure to one lane)
class VLD3LND<bits<4> op11_8, string OpcodeStr>

16
lib/Target/ARM/NEONPreAllocPass.cpp
View File

@@ -57,6 +57,22 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
NumRegs = 2;
return true;
case ARM::VLD2LNq16a:
case ARM::VLD2LNq32a:
FirstOpnd = 0;
NumRegs = 2;
Offset = 0;
Stride = 2;
return true;
case ARM::VLD2LNq16b:
case ARM::VLD2LNq32b:
FirstOpnd = 0;
NumRegs = 2;
Offset = 1;
Stride = 2;
return true;
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:

41
test/CodeGen/ARM/vldlane.ll
View File

@@ -5,6 +5,10 @@
%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
;CHECK: vld2lanei8:
;CHECK: vld2.8
@@ -49,11 +53,48 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
ret <2 x float> %tmp5
}
define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
;CHECK: vld2laneQi16:
;CHECK: vld2.16
%tmp1 = load <8 x i16>* %B
%tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
%tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1
%tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
;CHECK: vld2laneQi32:
;CHECK: vld2.32
%tmp1 = load <4 x i32>* %B
%tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2)
%tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1
%tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5
}
define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
;CHECK: vld2laneQf:
;CHECK: vld2.32
%tmp1 = load <4 x float>* %B
%tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
%tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1
%tmp5 = add <4 x float> %tmp3, %tmp4
ret <4 x float> %tmp5
}
declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32) nounwind readonly
declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32) nounwind readonly
declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32) nounwind readonly
declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8*, <2 x float>, <2 x float>, i32) nounwind readonly
declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32) nounwind readonly
declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32) nounwind readonly
declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind readonly
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }