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[NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185328 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski 2013-07-01 12:58:48 +00:00
parent d212db0cac
commit 30b13ebd0b
2 changed files with 16 additions and 1 deletions
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3
lib/Target/NVPTX/NVPTXISelLowering.cpp
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@ -2373,7 +2373,8 @@ static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, &Ops[0], DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, &Ops[0],
Ops.size(), MVT::i8, MemSD->getMemOperand()); Ops.size(), MVT::i8, MemSD->getMemOperand());
Results.push_back(NewLD.getValue(0)); Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
NewLD.getValue(0)));
Results.push_back(NewLD.getValue(1)); Results.push_back(NewLD.getValue(1));
} }
} }

14
test/CodeGen/NVPTX/ldu-i8.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
declare i8 @llvm.nvvm.ldu.global.i.i8(i8*)
define i8 @foo(i8* %a) {
; Ensure we properly truncate off the high-order 24 bits
; CHECK: ldu.global.u8
; CHECK: cvt.u32.u16
; CHECK: and.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 255
%val = tail call i8 @llvm.nvvm.ldu.global.i.i8(i8* %a)
ret i8 %val
}