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[x86] Teach the new vector shuffle lowering to lower v4i64 vector
shuffles using the AVX2 instructions. This is the first step of cutting in real AVX2 support. Note that I have spotted at least one bug in the test cases already, but I suspect it was already present and just is getting surfaced. Will investigate next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218338 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth
parent
8577eaf8e6
commit
30ce74b5e3
@ -7270,12 +7270,17 @@ static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
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return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
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DAG.getConstant(BlendMask, MVT::i8));
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case MVT::v4i64:
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case MVT::v8i32:
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assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
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// FALLTHROUGH
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case MVT::v2i64:
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case MVT::v4i32:
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// If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
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// that instruction.
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if (Subtarget->hasAVX2()) {
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int Scale = 4 / VT.getVectorNumElements();
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// Scale the blend by the number of 32-bit dwords per element.
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int Scale = VT.getScalarSizeInBits() / 32;
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BlendMask = 0;
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for (int i = 0, Size = Mask.size(); i < Size; ++i)
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if (Mask[i] >= Size)
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@ -9372,11 +9377,57 @@ static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
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assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
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// FIXME: Actually implement this using AVX2!!!
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V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
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V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
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return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
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DAG.getVectorShuffle(MVT::v4f64, DL, V1, V2, Mask));
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if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
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Subtarget, DAG))
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return Blend;
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// When the shuffle is mirrored between the 128-bit lanes of the unit, we can
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// use lower latency instructions that will operate on both 128-bit lanes.
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if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask)) {
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if (isSingleInputShuffleMask(Mask)) {
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int PSHUFDMask[] = {-1, -1, -1, -1};
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for (int i = 0; i < 2; ++i)
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if (Mask[i] >= 0) {
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PSHUFDMask[2 * i] = 2 * Mask[i];
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PSHUFDMask[2 * i + 1] = 2 * Mask[i] + 1;
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}
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return DAG.getNode(
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ISD::BITCAST, DL, MVT::v4i64,
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DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
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DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
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getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
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}
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
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return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
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if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
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}
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// AVX2 provides a direct instruction for permuting a single input across
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// lanes.
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if (isSingleInputShuffleMask(Mask))
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return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
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getV4X86ShuffleImm8ForMask(Mask, DAG));
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// Shuffle the input elements into the desired positions in V1 and V2 and
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// blend them together.
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int V1Mask[] = {-1, -1, -1, -1};
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int V2Mask[] = {-1, -1, -1, -1};
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int BlendMask[] = {-1, -1, -1, -1};
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for (int i = 0; i < 4; ++i)
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if (Mask[i] >= 0 && Mask[i] < 4) {
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V1Mask[i] = Mask[i];
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BlendMask[i] = i;
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} else if (Mask[i] >= 4) {
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V2Mask[i] = Mask[i] - 4;
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BlendMask[i] = i + 4;
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}
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V1 = DAG.getVectorShuffle(MVT::v4i64, DL, V1, DAG.getUNDEF(MVT::v4i64), V1Mask);
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V2 = DAG.getVectorShuffle(MVT::v4i64, DL, V2, DAG.getUNDEF(MVT::v4i64), V2Mask);
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return DAG.getVectorShuffle(MVT::v4i64, DL, V1, V2, BlendMask);
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}
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/// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
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@ -250,203 +250,305 @@ define <4 x double> @shuffle_v4f64_0167(<4 x double> %a, <4 x double> %b) {
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}
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define <4 x i64> @shuffle_v4i64_0001(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_0001
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; ALL: # BB#0:
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; ALL-NEXT: vunpcklpd {{.*}} # xmm1 = xmm0[0,0]
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; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_0001
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; AVX1: # BB#0:
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_0001
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[0,0,0,1]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0020(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_0020
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; ALL: # BB#0:
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; ALL-NEXT: vextractf128 $1, %ymm0, %xmm1
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; ALL-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0],xmm0[0]
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; ALL-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_0020
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0],xmm0[0]
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_0020
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[0,0,2,0]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0112(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_0112
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; ALL: # BB#0:
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; ALL-NEXT: vextractf128 $1, %ymm0, %xmm1
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; ALL-NEXT: vshufpd {{.*}} # xmm1 = xmm0[1],xmm1[0]
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; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_0112
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[1],xmm1[0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_0112
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[0,1,1,2]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 1, i32 2>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0300(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_0300
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; ALL: # BB#0:
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; ALL-NEXT: vextractf128 $1, %ymm0, %xmm1
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; ALL-NEXT: vblendpd {{.*}} # xmm1 = xmm0[0],xmm1[1]
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; ALL-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_0300
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vblendpd {{.*}} # xmm1 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_0300
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[0,3,0,0]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_1000(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_1000
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; ALL: # BB#0:
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; ALL-NEXT: vpermilpd {{.*}} # xmm1 = xmm0[1,0]
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; ALL-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_1000
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # xmm1 = xmm0[1,0]
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_1000
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[1,0,0,0]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_2200(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_2200
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; ALL: # BB#0:
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; ALL-NEXT: vextractf128 $1, %ymm0, %xmm1
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; ALL-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
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; ALL-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_2200
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_2200
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[2,2,0,0]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_3330(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_3330
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; ALL: # BB#0:
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; ALL-NEXT: vextractf128 $1, %ymm0, %xmm1
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; ALL-NEXT: vshufpd {{.*}} # xmm0 = xmm1[1],xmm0[0]
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; ALL-NEXT: vmovhlps {{.*}} # xmm1 = xmm1[1,1]
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; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_3330
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[1],xmm0[0]
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; AVX1-NEXT: vmovhlps {{.*}} # xmm1 = xmm1[1,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_3330
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[3,3,3,0]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_3210(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_3210
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; ALL: # BB#0:
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; ALL-NEXT: vextractf128 $1, %ymm0, %xmm1
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; ALL-NEXT: vpermilpd {{.*}} # xmm1 = xmm1[1,0]
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; ALL-NEXT: vpermilpd {{.*}} # xmm0 = xmm0[1,0]
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; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_3210
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpermilpd {{.*}} # xmm1 = xmm1[1,0]
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; AVX1-NEXT: vpermilpd {{.*}} # xmm0 = xmm0[1,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_3210
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[3,2,1,0]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0124(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_0124
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; ALL: # BB#0:
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; ALL-NEXT: vextractf128 $1, %ymm0, %xmm2
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; ALL-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
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; ALL-NEXT: vblendpd {{.*}} # xmm1 = xmm2[0],xmm1[1]
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; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_0124
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
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; AVX1-NEXT: vblendpd {{.*}} # xmm1 = xmm2[0],xmm1[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: @shuffle_v4i64_0124
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*}} # ymm1 = ymm1[0,1,2,0]
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; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7]
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; AVX2-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0142(<4 x i64> %a, <4 x i64> %b) {
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; ALL-LABEL: @shuffle_v4i64_0142
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; ALL: # BB#0:
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; ALL-NEXT: vextractf128 $1, %ymm0, %xmm2
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; ALL-NEXT: vunpcklpd {{.*}} # xmm2 = xmm2[0,0]
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; ALL-NEXT: vblendpd {{.*}} # xmm1 = xmm1[0],xmm2[1]
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; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; ALL-NEXT: retq
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; AVX1-LABEL: @shuffle_v4i64_0142
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vunpcklpd {{.*}} # xmm2 = xmm2[0,0]
|
||||
; AVX1-NEXT: vblendpd {{.*}} # xmm1 = xmm1[0],xmm2[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @shuffle_v4i64_0142
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm1 = ymm1[0,1,0,3]
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[0,1,2,2]
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <4 x i64> @shuffle_v4i64_0412(<4 x i64> %a, <4 x i64> %b) {
|
||||
; ALL-LABEL: @shuffle_v4i64_0412
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; ALL-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0]
|
||||
; ALL-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
|
||||
; ALL-NEXT: vblendpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
|
||||
; ALL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @shuffle_v4i64_0412
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0]
|
||||
; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
|
||||
; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @shuffle_v4i64_0412
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpshufd {{.*}} # ymm1 = ymm1[0,1,0,1,4,5,4,5]
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[0,1,1,2]
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5,6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <4 x i64> @shuffle_v4i64_4012(<4 x i64> %a, <4 x i64> %b) {
|
||||
; ALL-LABEL: @shuffle_v4i64_4012
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; ALL-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0]
|
||||
; ALL-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
|
||||
; ALL-NEXT: vblendpd {{.*}} # xmm0 = xmm1[0],xmm0[1]
|
||||
; ALL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @shuffle_v4i64_4012
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0]
|
||||
; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
|
||||
; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm1[0],xmm0[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @shuffle_v4i64_4012
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpshufd {{.*}} # ymm0 = ymm0[0,1,0,1,4,5,4,5]
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm1[0,1],ymm0[2,3,4,5,6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <4 x i64> @shuffle_v4i64_0145(<4 x i64> %a, <4 x i64> %b) {
|
||||
; ALL-LABEL: @shuffle_v4i64_0145
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @shuffle_v4i64_0145
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @shuffle_v4i64_0145
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm1 = ymm1[0,1,0,1]
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <4 x i64> @shuffle_v4i64_0451(<4 x i64> %a, <4 x i64> %b) {
|
||||
; ALL-LABEL: @shuffle_v4i64_0451
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vpermilpd {{.*}} # xmm2 = xmm1[1,0]
|
||||
; ALL-NEXT: vblendpd {{.*}} # xmm2 = xmm2[0],xmm0[1]
|
||||
; ALL-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
|
||||
; ALL-NEXT: vblendpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
|
||||
; ALL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @shuffle_v4i64_0451
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpermilpd {{.*}} # xmm2 = xmm1[1,0]
|
||||
; AVX1-NEXT: vblendpd {{.*}} # xmm2 = xmm2[0],xmm0[1]
|
||||
; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
|
||||
; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @shuffle_v4i64_0451
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpshufd {{.*}} # ymm1 = ymm1[0,1,0,1,4,5,4,5]
|
||||
; AVX2-NEXT: vpshufd {{.*}} # ymm0 = ymm0[0,1,2,3,4,5,6,7]
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 1>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <4 x i64> @shuffle_v4i64_4501(<4 x i64> %a, <4 x i64> %b) {
|
||||
; ALL-LABEL: @shuffle_v4i64_4501
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @shuffle_v4i64_4501
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @shuffle_v4i64_4501
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[0,1,0,1]
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <4 x i64> @shuffle_v4i64_4015(<4 x i64> %a, <4 x i64> %b) {
|
||||
; ALL-LABEL: @shuffle_v4i64_4015
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vpermilpd {{.*}} # xmm2 = xmm0[1,0]
|
||||
; ALL-NEXT: vblendpd {{.*}} # xmm2 = xmm2[0],xmm1[1]
|
||||
; ALL-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
|
||||
; ALL-NEXT: vblendpd {{.*}} # xmm0 = xmm1[0],xmm0[1]
|
||||
; ALL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @shuffle_v4i64_4015
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpermilpd {{.*}} # xmm2 = xmm0[1,0]
|
||||
; AVX1-NEXT: vblendpd {{.*}} # xmm2 = xmm2[0],xmm1[1]
|
||||
; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
|
||||
; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm1[0],xmm0[1]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @shuffle_v4i64_4015
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpshufd {{.*}} # ymm1 = ymm1[0,1,2,3,4,5,6,7]
|
||||
; AVX2-NEXT: vpshufd {{.*}} # ymm0 = ymm0[0,1,0,1,4,5,4,5]
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm1[0,1],ymm0[2,3,4,5],ymm1[6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 5>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <4 x i64> @stress_test1(<4 x i64> %a, <4 x i64> %b) {
|
||||
; ALL-LABEL: @stress_test1
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vpermilpd {{.*}} # xmm0 = xmm1[1,0]
|
||||
; ALL-NEXT: vpermilpd {{.*}} # xmm0 = xmm0[1,0]
|
||||
; ALL-NEXT: vextractf128 $1, %ymm1, %xmm1
|
||||
; ALL-NEXT: vmovhlps {{.*}} # xmm1 = xmm1[1,1]
|
||||
; ALL-NEXT: vpermilpd {{.*}} # xmm1 = xmm1[1,0]
|
||||
; ALL-NEXT: vblendpd {{.*}} # xmm1 = xmm1[0],xmm0[1]
|
||||
; ALL-NEXT: vpermilpd {{.*}} # xmm0 = xmm0[1,0]
|
||||
; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @stress_test1
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpermilpd {{.*}} # xmm0 = xmm1[1,0]
|
||||
; AVX1-NEXT: vpermilpd {{.*}} # xmm0 = xmm0[1,0]
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
|
||||
; AVX1-NEXT: vmovhlps {{.*}} # xmm1 = xmm1[1,1]
|
||||
; AVX1-NEXT: vpermilpd {{.*}} # xmm1 = xmm1[1,0]
|
||||
; AVX1-NEXT: vblendpd {{.*}} # xmm1 = xmm1[0],xmm0[1]
|
||||
; AVX1-NEXT: vpermilpd {{.*}} # xmm0 = xmm0[1,0]
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @stress_test1
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm1[3,1,1,0]
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[3,1,2,3]
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm1 = ymm1[3,3,1,3]
|
||||
; AVX2-NEXT: vpshufd {{.*}} # ymm1 = ymm1[2,3,2,3,6,7,6,7]
|
||||
; AVX2-NEXT: vpermq {{.*}} # ymm0 = ymm0[0,1,1,0]
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm1[0,1],ymm0[2,3,4,5,6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%c = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 1, i32 1, i32 0>
|
||||
%d = shufflevector <4 x i64> %c, <4 x i64> undef, <4 x i32> <i32 3, i32 undef, i32 2, i32 undef>
|
||||
%e = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 3, i32 1, i32 undef>
|
||||
@ -456,24 +558,38 @@ define <4 x i64> @stress_test1(<4 x i64> %a, <4 x i64> %b) {
|
||||
}
|
||||
|
||||
define <4 x i64> @insert_reg_and_zero_v4i64(i64 %a) {
|
||||
; ALL-LABEL: @insert_reg_and_zero_v4i64
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovq %rdi, %xmm0
|
||||
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1
|
||||
; ALL-NEXT: vblendpd {{.*}} # ymm0 = ymm0[0],ymm1[1,2,3]
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @insert_reg_and_zero_v4i64
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vmovq %rdi, %xmm0
|
||||
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1
|
||||
; AVX1-NEXT: vblendpd {{.*}} # ymm0 = ymm0[0],ymm1[1,2,3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @insert_reg_and_zero_v4i64
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vmovq %rdi, %xmm0
|
||||
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%v = insertelement <4 x i64> undef, i64 %a, i64 0
|
||||
%shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
|
||||
ret <4 x i64> %shuffle
|
||||
}
|
||||
|
||||
define <4 x i64> @insert_mem_and_zero_v4i64(i64* %ptr) {
|
||||
; ALL-LABEL: @insert_mem_and_zero_v4i64
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vmovq (%rdi), %xmm0
|
||||
; ALL-NEXT: vxorpd %ymm1, %ymm1, %ymm1
|
||||
; ALL-NEXT: vblendpd {{.*}} # ymm0 = ymm0[0],ymm1[1,2,3]
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @insert_mem_and_zero_v4i64
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vmovq (%rdi), %xmm0
|
||||
; AVX1-NEXT: vxorpd %ymm1, %ymm1, %ymm1
|
||||
; AVX1-NEXT: vblendpd {{.*}} # ymm0 = ymm0[0],ymm1[1,2,3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @insert_mem_and_zero_v4i64
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vmovq (%rdi), %xmm0
|
||||
; AVX2-NEXT: vpxor %ymm1, %ymm1, %ymm1
|
||||
; AVX2-NEXT: vpblendd {{.*}} # ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
|
||||
; AVX2-NEXT: retq
|
||||
%a = load i64* %ptr
|
||||
%v = insertelement <4 x i64> undef, i64 %a, i64 0
|
||||
%shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
|
||||
|
||||
@ -645,10 +645,15 @@ define <8 x i32> @shuffle_v8i32_70000000(<8 x i32> %a, <8 x i32> %b) {
|
||||
}
|
||||
|
||||
define <8 x i32> @shuffle_v8i32_01014545(<8 x i32> %a, <8 x i32> %b) {
|
||||
; ALL-LABEL: @shuffle_v8i32_01014545
|
||||
; ALL: # BB#0:
|
||||
; ALL-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[0,0,2,2]
|
||||
; ALL-NEXT: retq
|
||||
; AVX1-LABEL: @shuffle_v8i32_01014545
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[0,0,2,2]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: @shuffle_v8i32_01014545
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpshufd {{.*}} # ymm0 = ymm0[0,1,0,1,4,5,4,5]
|
||||
; AVX2-NEXT: retq
|
||||
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 5, i32 4, i32 5>
|
||||
ret <8 x i32> %shuffle
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user